Multiphase power converter circuit and method

ABSTRACT

A multiphase power converter circuit includes at least two single phase power converter circuits. Each single phase power converter circuit includes at least one converter series circuit with a number of converter units. The converter series circuit is configured to output a series circuit output current. A synchronization circuit is configured to generate at least one synchronization signal. At least one of the converter units is configured to generate an output current such that at least one of a frequency and a phase of the output current is dependent on the synchronization signal.

TECHNICAL FIELD

Embodiments of the present invention relate to a power converter circuit, a power supply system with a power converter circuit, and a method for operating a power converter circuit.

BACKGROUND

With an increasing interest in sustainable energy production there is a focus on using photovoltaic modules for producing electric power. Photovoltaic (PV) modules include a plurality of photovoltaic (PV) cells, that are also known as solar cells. Since the output voltage of one cell is relatively low, a PV module usually includes a string with a plurality of series connected solar cells, such as between 50 to 100 cells connected in series, or even several such strings connected in parallel.

A PV module provides a DC supply voltage, while power grids, such as national power grids, have an AC supply voltage. In order to supply the energy provided by a PV module to the power grid it is, therefore, necessary to convert the DC voltage of the PV module into an AC voltage that is consistent with the AC supply voltage of the power grid. Several concepts are known to convert DC voltages provided by DC power sources into an AC voltage and an AC current, respectively.

A first approach for converting the PV module DC voltage into a power grid AC voltage includes connecting several PV modules in series so as to obtain a DC voltage that is higher than the peak voltage of the power grid AC voltage, and converting the DC voltage into the AC voltage using a DC/AC converter. The amplitude of the DC voltage is typically between 200V and 1000V. High DC voltages, however, are critical in terms of the occurrence of electric arcs.

According to a second approach, a plurality of DC/AC converters are provided, where each of these converters is connected to a PV module. The individual converters have their AC voltage outputs connected in parallel and each of these converters generates an AC voltage that is consistent with the power grid AC supply voltage from the DC voltage provided by the string of solar cells. The DC voltage provided by one PV module usually has an amplitude in the range of between 20V and 100V, depending on the number of cells that are connected in series within one module and depending on the technology used to implement the solar cells, while the peak voltage of the power grid AC voltage is about 155V or 325V, depending on the country. However, due to the large difference between input and output voltages these converters have a disadvantage in terms of efficiency.

There is, therefore, a need for a power converter circuit that is capable of efficiently transforming relatively low DC supply voltages into an AC output signal that is consistent with a power grid voltage.

SUMMARY OF THE INVENTION

A first aspect relates to a multiphase power converter circuit with at least two single phase power converter circuits. Each single phase power converter circuit includes at least one converter series, and a synchronization circuit. The at least one converter series circuit includes a plurality of converter units, and is configured to output a series circuit output current. The synchronization circuit is configured to generate at least one synchronization signal. At least one of the plurality of converter units is configured to generate an output current such that at least one of a frequency and a phase of the output current is dependent on the synchronization signal.

A second aspect relates to a method. The method includes generating at least one synchronization signal by a synchronization circuit, outputting a series circuit output current by at least one converter series circuit of each of at least two single phase converter circuits in a multiphase converter, wherein the at least one converter series circuit comprises a plurality of converter units, and outputting an out-put current by at least one of the plurality of converter units such that at least one of a frequency and a phase of the output current is dependent on the synchronization signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Examples will now be explained with reference to the drawings. The drawings serve to illustrate the basic principle, so that only aspects necessary for under-standing the basic principle are illustrated. The drawings are not to scale. In the drawings the same reference characters denote like signals and circuit components:

FIG. 1 schematically illustrates a power converter circuit including a plurality of DC/AC converter units connected in series and a voltage measurement circuit;

FIG. 2, which includes FIGS. 2A-2C, illustrates different embodiments of photovoltaic arrays, each including at least one solar cell;

FIG. 3 schematically illustrates a power converter circuit including a plurality of DC/AC converter units connected in series and a voltage measurement circuit including a plurality of measurement units connected in series;

FIG. 4 which includes FIGS. 4A-4D illustrates different embodiments of measurement units;

FIG. 5 shows a block diagram illustrating a first embodiment of one DC/AC converter unit, including a DC/AC converter and a control circuit;

FIG. 6 illustrates an embodiment of the DC/AC converter of FIG. 5 in detail;

FIG. 7, which includes FIGS. 7A to 7C, illustrates different embodiments of switches that may be used in the DC/AC converter of FIG. 6;

FIG. 8 illustrates a first embodiment of the control circuit of one DC/AC converter unit;

FIG. 9 illustrates a first branch of the control circuit of FIG. 8 in detail;

FIG. 10 illustrates a second embodiment of the control circuit of one DC/AC converter unit;

FIG. 11 shows a block diagram illustrating a second embodiment of one converter unit, including a DC/DC converter, a maximum power point tracker, a DC/AC converter, and a control circuit;

FIG. 12 illustrates an embodiment of the DC/DC converter implemented as a boost converter;

FIG. 13 schematically illustrates a control circuit of the DC/DC converter of FIG. 12;

FIG. 14 illustrates an embodiment of the DC/DC converter implemented as a buck converter;

FIG. 15 illustrates a further embodiment of the control circuit of one DC/AC converter;

FIG. 16 illustrates an embodiment of the DC/DC converter implemented with two interleaved boost converter stages;

FIG. 17 illustrates a first embodiment of a control circuit for the DC/DC converter of FIG. 16;

FIG. 18 illustrates a second embodiment of a control circuit for the DC/DC converter of FIG. 16;

FIG. 19 shows a block diagram illustrating a further embodiment of one DC/AC converter unit including a buck converter and an unfolding bridge;

FIG. 20 shows timing diagrams illustrating the operating principle of the DC/AC converter unit of FIG. 19;

FIG. 21 illustrates a first embodiment of a controller implemented in the DC/AC converter unit of FIG. 19;

FIG. 22 illustrates a second embodiment of a controller implemented in the DC/AC converter unit of FIG. 19;

FIG. 23 illustrates an embodiment of a power converter circuit having a plurality of converter units organized in two series circuits being connected in parallel;

FIG. 24 illustrates a further embodiment of the synchronization circuit;

FIG. 25 illustrates an embodiment of a transmission circuit in the synchronization circuit of FIG. 24;

FIG. 26 illustrates a further embodiment of one converter unit;

FIG. 27 illustrates a first embodiment of a signal generator in the converter unit of FIG. 26;

FIG. 28 illustrates timing diagrams of signals occurring in the signal generator of FIG. 27;

FIG. 29 illustrates a first embodiment of a signal generator in the converter unit of FIG. 26;

FIG. 30 schematically illustrates two possible operation modes of the power converter circuit;

FIG. 31 illustrates an embodiment of a power converter circuit including an operation mode controller;

FIG. 32 illustrates an embodiment of a converter unit including an operation mode unit;

FIG. 33 illustrates a first embodiment of a transfer from a first operation mode to a second operation mode;

FIG. 34 illustrates a second embodiment of a transfer from a first operation mode to a second operation mode;

FIG. 35 illustrates a further embodiment of a power converter circuit;

FIG. 36 illustrates an embodiment of a converter unit implemented in the power converter circuit of FIG. 35;

FIG. 37 illustrates a further embodiment of a converter unit;

FIG. 38 illustrates an embodiment of a power converter circuit including an unfolding circuit connected between a series circuit with converter units and output terminals;

FIG. 39 shows timing diagrams illustrating the operating principle of the power converter circuit of FIG. 38;

FIG. 40 illustrates an embodiment of the unfolding circuit;

FIG. 41 illustrates a first embodiment of a converter unit in the power converter circuit of FIG. 38;

FIG. 42 illustrates a second embodiment of a converter unit in the power converter circuit of FIG. 38;

FIG. 43 illustrates a third embodiment of a converter unit in the power converter circuit of FIG. 38;

FIG. 44 illustrates a first embodiment of a power converter circuit including at least one transformer;

FIG. 45 illustrates a second embodiment of a power converter circuit including at least one transformer;

FIG. 46 schematically illustrates one embodiment of a DC/DC converter including a transformer;

FIG. 47 illustrates an embodiment of a DC/DC converter having a two-transistor forward (TTF) topology;

FIG. 48 illustrates an embodiment of a DC/DC converter having a phase-shift (PS) zero-voltage-switching (ZVS) converter topology;

FIG. 49 illustrates an embodiment of a DC/DC converter having a flyback converter topology;

FIG. 50 illustrates an embodiment of a DC/DC converter having an LLC converter topology;

FIG. 51 illustrates one embodiment of a DC/AC converter including a transformer;

FIG. 52 illustrates one embodiment of a power converter circuit with a plurality of DC/DC converters that share one transformer;

FIG. 53 illustrates yet another embodiment of a power converter circuit with a plurality of DC/DC converters that share one transformer;

FIG. 54 illustrates one embodiment of a converter unit including a converter stage with an inverting buck boost topology;

FIG. 55 shows timing diagrams of an input voltage, an output voltage, and an output current of the converter stage shown in FIG. 54, in one operation mode;

FIG. 56 shows timing diagrams of a switch drive signal and of a current through an inductive element in the inverting buck boost converter shown in FIG. 54, one operation mode;

FIG. 57 illustrates a modification of the converter stage shown in FIG. 54;

FIG. 58 shows timing diagrams of a switch drive signal and of a current through an inductive element in the converter stage shown in FIG. 58, in one operation mode;

FIG. 59 illustrates a further embodiment of a converter unit including a converter stage with an inverting buck boost topology;

FIG. 60 illustrates one embodiment of a 3-phase power converter circuit with three single phase power converter circuits;

FIG. 61 illustrates another embodiment of a 3-phase power converter circuit with three single phase power converter circuits;

FIG. 62 schematically shows timing diagrams of output currents of the 3-phase power converter circuit shown in FIG. 60;

FIG. 63 illustrates another embodiment of a 3-phase power converter circuit with three single phase power converter circuits;

FIG. 64 schematically illustrates three power converter units of three different single phase power converter circuits coupled to one power source;

FIG. 65 shows one embodiment of one of the three power converter units shown in FIG. 64;

FIG. 66 shows one feature of the power converter unit shown in FIG. 65;

FIG. 67 shows one feature of the power converter unit shown in FIG. 65;

FIG. 68 shows another embodiment of one of the three power converter units shown in FIG. 64;

FIG. 69 schematically illustrates three power converter units of three different single phase power converter circuits coupled to one power source;

FIG. 70 shows one embodiment of one converter stage shown in FIG. 69;

FIG. 71 illustrates one embodiment of a connection circuit that may be used in a 3-phase power converter circuit; and

FIG. 72 illustrates another embodiment of a connection circuit that may be used in a 3-phase power converter circuit.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figures being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.

In the following, embodiments of the present invention will be explained in a specific context, namely in the context of converting electrical power or electrical voltages provided by a plurality of photovoltaic arrays into an alternating current, specifically an alternating current to be supplied to a power grid. The alternating current and an alternating power grid voltage will also be referred to as AC current and AC power grid voltage, respectively, in the following. However, this is only an example, embodiments of the invention may be employed in a wide range of applications in which a conversion of direct voltages and direct currents into an AC voltage and an AC current is required. In the following, direct voltages and direct currents will also be referred to as DC voltages and DC currents, respectively. Any type of DC power source may be used instead of an photovoltaic array, such as a fuel cell. It is even possible, to employ DC power source of different types, such as photovoltaic arrays and fuel cells, in one application.

FIG. 1 illustrates a first embodiment of a power converter circuit (power inverter circuit) 4 for converting a plurality of n (at least two) DC input voltages V3 ₁, V3 ₂, V3 _(n) into one AC output voltage v1 and one AC output current i_(OUT), respectively. It should be noted in this connection that throughout the drawings DC voltages and DC currents will be denoted using capital letters “V” and “I,” while AC voltages and AC currents will be denoted using lowercase letters “v” and “i.” The power converter circuit includes a plurality of n (at least two) converter units (inverter units) 2 ₁, 2 ₂, 2 _(n), with n≧2. Each of these converter units includes an input with input terminals 21 ₁, 22 ₁; 21 ₂, 22 ₂; and 21 _(n), 22 _(n) that are configured to be coupled to a DC power source 3 ₁, 3 ₂, 3 _(n). In FIG. 1, besides the power converter circuit 1 with the converter units 2 ₁, 2 ₂, 2 _(n) DC power sources 3 ₁, 3 ₂, 3 _(n) are also illustrated. These DC power sources 3 ₁, 3 ₂, 3 _(n) together with the power converter circuit 1 form an AC power supply system or an AC current supply system. The DC power sources 3 ₁, 3 ₂, 3 _(n) are implemented as photovoltaic (PV) modules in the embodiment illustrated in FIG. 1. However employing PV modules as DC power sources is only an example. Any other type of DC power source, such as a power source including fuel cells, may be used as well. It is even possible to employ different types of DC power sources in one power supply system.

Each of the converter units 2 ₁, 2 ₂, 2 _(n) further includes an output with output terminals 23 ₁, 24 ₁; 23 ₂, 24 ₂; and 23 _(n), 24 _(n). The converter units 2 ₁, 2 ₂, 2 _(n) are connected in series (cascaded) between an output with output terminals 11, 12 of the power converter circuit 1. For this, a first converter unit 2 ₁ has a first output terminal 23 ₁ coupled to a first output terminal 11 of the power converter circuit 1 and a last converter unit 2 _(n) in the cascade has a second output terminal 24 _(n) coupled to a second output terminal 12 of the power converter circuit 1. Further, each of the first output terminals (other than output terminal 23 ₁) are connected to one second output terminal (other than output terminal 24 _(n)) of another converter unit.

The output terminals 11, 12 of the power converter circuit 1 can be configured to receive a voltage v1. For example, the output terminals 11, 12 are configured to be connected to a power grid, so that the external voltage v1 corresponds to a grid voltage or, more specifically, corresponds to one phase of the power grid. In FIG. 1, the power grid is represented by a voltage source 100 and a load Z connected in parallel with the power source 100. The voltage source 100 of the power grid represents a plurality of AC voltage sources in the power grid, and load Z represents a plurality of loads connected to the power sources in the power grid. The power grid defines the AC voltage v1 between the output terminal 11, 12. Since this voltage v1 is defined by an external source, such as the power grid, this voltage will be referred to as external AC voltage v1 in the following.

Each of the converter units 2 ₁, 2 ₂, 2 _(n) has an AC output voltage v2 ₁, v2 ₂, v2 _(n) between its output terminals 23 ₁, 24 ₁, 23 ₂, 24 ₂, 23 _(n), 24 _(n). By having the converter units 2 ₁, 2 ₂, 2 _(n) connected in series, the sum of the individual AC output voltages v2 ₁, v2 ₂, v2 _(n) of the converter units 2 ₁, 2 ₂, 2 _(n) corresponds to the external voltage v1 when the power converter circuit 1 is in the steady state, that is.

$\begin{matrix} {{v\; 1} = {\sum\limits_{i = 1}^{n}{v\;{2_{i}.}}}} & (1) \end{matrix}$

Each power converter unit 2 ₁, 2 ₂, 2 _(n) further includes an output capacitance (output capacitor) C₁, C₂, C_(n) connected between the individual output terminals 23 ₁, 24 ₁, 23 ₂, 24 ₂, 23 _(n), 24 _(n) and provides an output current i1 ₁, i1 ₂, i1 _(n). The output current of one converter unit 2 ₁, 2 ₂, 2 _(n) is the current received at a circuit node common to the output capacitance C₁, C₂, C_(n) and one of the output terminals. For example, in the first converter unit 2 ₁, the output current of the converter unit 2 ₁ is the current flowing into the circuit node at which the output capacitor C₁ is connected to the first output terminal 23 ₁. The current flowing from the first output terminal 23 ₁ of the first converter unit 2 ₁ is the output current of the series circuit with the plurality of converter units 2 ₁-2 _(n) and will be referred to as converter circuit output current i_(OUT) or series circuit output current I_(OUT) in the following. This current corresponds to the current flowing between the individual converter units 2 ₁-2 _(n). The output capacitances C₁, C₂, C_(n) are part of the individual converter units 2 ₁, 2 ₂, 2 _(n) and can be implemented in many different ways as will be explained with reference to several examples herein below.

In the steady state, the AC output currents i1 ₁, i1 ₂, i1 _(n) or, more precisely, the rms values of the AC output currents i1 ₁, i1 ₂, i1 _(n), correspond to the power converter circuit output current i_(OUT) or the rms value of the output current i_(OUT), respectively, so that there is very little to no rms current into the output capacitors C₁-C_(n). However, there can be situations in which the output currents i1 ₁, i1 ₂, i1 _(n) of the individual converter units 2 ₁, 2 ₂, 2 _(n) change and in which the output currents i1 ₁, i1 ₂, i1 _(n) are mutually different until the system has settled at new (equal) output currents i1 ₁, i1 ₂, i1 _(n). This is explained in further detail below.

The power converter circuit 1 further includes a synchronization circuit 10 connected between the output terminals 11, 12 of the power converter circuit 1. The synchronization circuit 10 is configured to provide at least one synchronization signal S_(v1). According to one embodiment, the synchronization signal is an alternating (AC) signal having a phase and a frequency dependent on the phase and the frequency, respectively, of the external AC voltage v1.

The individual converter units 2 ₁, 2 ₂, 2 _(n) are each configured to receive one synchronization signal S_(v1). In the embodiment illustrated in FIG. 1, the individual converter units 2 ₁, 2 ₂, 2 _(n) receive the same synchronization signal S_(v1). However, this is only an example. It is also possible to generate one synchronization signal for each of the converter units 2 ₁, 2 ₂, 2 _(n). An embodiment of a synchronization circuit 10 that generates one synchronization signal for each converter unit 2 ₁-2 _(n) is explained with reference to FIG. 3 herein below.

The at least one synchronization signal S_(v1) can be transmitted to the individual converter units 2 ₁, 2 ₂, 2 _(n) in different ways. Referring to FIG. 1, a signal transmission bus can be provided through which the at least one synchronization signal S_(v1) is transmitted to the individual converter units 2 ₁, 2 ₂, 2 _(n). According to a further embodiment (not illustrated in FIG. 1), there is a dedicated transmission path between the voltage synchronization circuit 10 and each of the converter units 2 ₁, 2 ₂, 2 _(n). The signal transmission bus or the signal transmission paths can be implemented like conventional signal transmission buses or like conventional signal transmission paths. The signal bus or the signal paths may include level shifter or other means to transmit the at least one synchronization signal from the synchronization circuit 10 to the individual converter units 2 ₁, 2 ₂, 2 _(n) that (due to being connected in series) have different reference potentials or different voltage domains.

The individual converter units 2 ₁, 2 ₂, 2 _(n) each include at least one internal control loop which will be explained in further detail herein below. The control loop of each converter unit 2 ₁, 2 ₂, 2 _(n) is configured to have each converter unit 2 ₁, 2 ₂, 2 _(n) generate the corresponding output current i1 ₁, i1 ₂, i1 _(n), such that there is a given phase difference between the phase as represented by the at least one synchronization signal S_(v1), and the phase of its AC output current i1 ₁, i1 ₂, i1 _(n). According to one embodiment, the synchronization signal S_(v1) is in phase with the external AC voltage v1 and the individual output currents i1 ₁, i1 ₂, i1 _(n) are generated to be in phase with the synchronization signal S_(v1) and, therefore, the external AC voltage v1, so that the phase difference is zero. According to another embodiment, the phase difference is not zero. When setting the difference to a value other than zero, reactive power is fed into the power grid. This may help to stabilize the external AC voltage, which is, e.g., a power grid.

In FIG. 1, same features of the DC voltage sources 3 ₁, 3 ₂, 3 _(n) have the same reference characters, where the reference characters of the individual DC voltage sources 3 ₁, 3 ₂, 3 _(n) can be distinguished from each other by subscript indices “1,” “2,” “n.” Equivalently, same features of the converter units 2 ₁, 2 ₂, 2 _(n) have the same reference characters that can be distinguished by subscript indices, “1” for the first converter unit 2 ₁, “2” for the second converter unit 2 ₂ and “n” for the n-th converter unit 2 _(n). In the following, when explanations equivalently apply to each of the DC sources 2 ₁, 2 ₂, 2 _(n) or to each of the converter units 2 ₁, 2 ₂, 2 _(n), reference characters will be used without indices. In the following, reference character 2, for example, represents an arbitrary one of the converter units, reference character 23 represents a first output terminal of an arbitrary one of the converter units, reference character i1 denotes the output current of an arbitrary converter unit 2, reference character denotes the output capacitance C of an arbitrary converter unit 2, and so on.

The power converter of FIG. 1 includes n=3 converter units 2. However, having n=3 converter units is only an example. Any number n of converter units 2, wherein n>1, can be connected in series to form the power converter circuit 1.

Besides the internal control loops of the converter units 2 the power converter circuit 1 does not require an outer control loop connected to the individual converter units 2 and/or additional communication paths between the individual converter units 2, when the power converter circuit 1 is in the steady state. When the power converter circuit 1 is in the steady state the system can be defined by equation (1) and one further equation for each of the converter units 2: v2_(RMS) ·i1_(RMS) =V3·I3  (2), where v2 _(rms) denotes the RMS (route mean square) value of the output voltage v2 of one converter units 2, i1 _(RMS) denotes the RMS value of the output current i1 of one converter unit, V3 denotes the input voltage and I3 denotes the input current of the converter unit 2. It should be noted that (very low) losses may occur in each converter unit 2. For the sake of simplicity, these losses are not considered in equation (2). In the steady state, the RMS values of the individual output currents i1 _(RMS) are equal and correspond to the rms value of the power converter circuit output current i_(OUT-RMS), that is: i1_(RMS) =i1_(OUT-RMS)  (3), Since equations (2) and (3) is valid for each of the individual converter units, there are n equations, each of these equations describing the relationship between the input power and the average output power of each of the converter units 2, where the input power Pin is given as Pin=V3·I3  (4), and the output power Pout is given as Pout=v2_(RMS) ·i1_(RMS)  (5).

The input power Pin of each of the individual converter units 2 and the input volt-age V3 and the input current I3, respectively, are external parameters given by the individual DC power sources 3. The external AC voltage v1 between the output terminals 11, 12 is defined by the power grid.

Thus, there are n+1 variables in the power converter circuit 1, namely the n output voltages v2 of the individual converter units 2 and the (equal) output currents i1. However, referring to equations (1) and (2) the system is defined by n+1 equations, so that each of the n+1 variables is determined when the system is in its steady state. Besides having each of the converters 2 generate its AC output cur-rent i1 such that that there is a given phase difference (such as zero) between the AC output current i1 and the external AC voltage no additional control or regulation mechanism is required. When the output currents i1 of the individual converter units 2 are in phase with the external AC voltage v1 the real output power of each converter unit equals the apparent output power, so that the reactive output power is zero. The individual converter units 2 control their output currents i1 dependent on the phase information as represented by the at least one synchronization signal Sv1 and control their output current such that the input power received at the input terminals 21, 22 equals the output power at the output terminals 23, 24.

The DC power sources 3 implemented as PV arrays are only schematically illustrated in FIG. 1. These PV arrays each include at least one solar cell. Some exemplary embodiments of PV arrays including at least one solar cell are illustrated in FIGS. 2A to 2C. FIG. 2A illustrates a first embodiment. In this embodiment, the PV array 3 includes only one solar cell 31. Referring to a further embodiment illustrated in FIG. 2B, one PV array 3 includes a string of m solar cells 31, 3 m wherein m>1, connected in series. According to yet another embodiment illustrated in FIG. 2C, p strings of solar cells are connected in parallel, wherein p>1. Each of the strings includes m solar cells 31 ₁, 3 m ₁, 31 _(p), 3 m _(p). However, the embodiments illustrated in FIGS. 2A to 2C are only exemplary. Many other solar cell arrangements may be used as well as a DC source 3.

FIG. 3 illustrates an embodiment of a power converter circuit that includes a synchronization circuit 10 implemented as a voltage measurement circuit with a plurality of measurement units 101, 10 ₂, 10 _(n). The individual measurement units 10 ₁, 10 ₂, 10 _(n) are connected in series between the output terminals 11, 12. For simplicity of the illustration, the output capacitances (C₁-C_(n) in FIG. 1) are not illustrated in FIG. 3. The plurality of measurement units 10 ₁, 10 ₂, 10 _(n) forms a voltage divider, wherein a voltage drop v1 ₁, v1 ₂, v1 _(n) across each of the measurement units 10 ₁, 10 ₂, 10 _(n) is a function of the external AC voltage v1 and includes an information on the frequency and the phase of the external AC voltage v1. In this embodiment, each converter unit 2 ₁, 2 ₂, 2 _(n) has a synchronization input with two input terminals 25 ₁, 26 ₁, 25 ₂, 26 ₂, 25 _(n), 26 _(n), and each converter unit 2 ₁, 2 ₂, 2 _(n) has the synchronization input terminals coupled to one measurement unit 10 ₁, 10 ₂, 10 _(n), so as to receive one measurement voltage v1 ₁, v1 ₂, v1 _(n) as the synchronization signal.

In the embodiment illustrated in FIG. 3, the number of measurement units 101, 102, 10 n corresponds to the number of converter units 21, 22, 2 n, so that each measurement unit 101, 102, 10 n is associated with one converter unit 21, 22, 2 n. However, this is only an example. According to a further embodiment (not illustrated) the measurement voltage provided by one measurement unit is received by two or more converter units.

The individual measurement units 10 ₁, 10 ₂, 10 _(n) can be implemented in many different ways. Some examples are explained with reference to FIGS. 4A to 4D below. In these FIGS. 4A to 4D, reference character 10 _(i) denotes an arbitrary one of the measurement units 10 ₁, 10 ₂, 10 _(n) illustrated in FIG. 3.

Referring to FIG. 4A, one measurement unit 10 _(i) may include a resistor 101 connected between the terminals of the measurement unit 10 _(i) that serve to connect the individual measurement units (10 ₁-10 _(n) in FIG. 3) in series and that serve to couple the individual measurement units to the converter units (2 ₁-2 _(n) in FIG. 3). According to one embodiment, the resistances of the resistors 101 in the individual measurement units 10 _(i) are equal or at least approximately equal. In this case, the absolute values of the measurement voltages v1 _(i) provided by the individual measurement units 10 _(i) are equal. In a measurement circuit 10 that includes measurement units 10 _(i) implemented with a resistor 101, the individual measurement voltages v1 _(i) are proportional to the output voltage v1.

In a measurement circuit 10 with measurement units 10 _(i) including resistors, the individual measurement units 10 i form a resistive voltage divider. Referring to a further embodiment illustrated in FIG. 4B, the individual measurement units 10 _(i) each include a capacitor 102 instead of a resistor. In this case, the individual measurement units 10 _(i) form a capacitive voltage divider between the output terminals 11, 12.

Referring to FIG. 4C, that illustrates a further embodiment, each measurement unit 10, can be implemented with a parallel circuit including a resistor 101 and a capacitor 102.

Referring to FIG. 4D, that illustrates yet another embodiment of one measurement unit 10 _(i), each measurement unit or at least some of the measurement units can be implemented with a voltage divider having a first voltage divider 101 and a second voltage divider element 102. These voltage divider elements are implemented as resistors in the embodiment according to FIG. 4D. However, these voltage divider elements 101, 102 could also be implemented as capacitors or as combinations with at least one resistor and at least one capacitor. In this embodiment, the measurement voltage v1 _(i) is not the voltage across the measurement unit 10 _(i), but is the voltage across the first voltage divider element 101, so that the measurement voltage v1 _(i) is a fraction of the voltage across the measurement unit 10 _(i).

It should be noted that implementing the synchronization circuit 10 as a voltage measurement circuit that generates the synchronization signal S_(v1) to be in phase with the external AC voltage v1 is only an example. Examples of other synchronization circuits are explained herein further below.

FIG. 5 illustrates a first embodiment of a converter unit 2 for converting the DC input voltage provided by one DC source (not shown in FIG. 3) into an AC output voltage v2. The converter unit 2 includes a DC/AC converter 4 connected between the input terminals 23, 22 and the output terminals 23, 24. The DC/AC converter receives the DC voltage V3 provided by the DC power source as an input voltage and the DC supply current I3 of the DC power source as an input current. The DC/AC converter 4 further receives a reference signal S_(REF), which may be an alternating signal having a frequency and a phase. The DC/AC converter 4 is configured to generate the AC output current i1 dependent on the reference signal S_(REF) such that a frequency and a phase of the output current i1 correspond to a frequency and a phase, respectively, of the synchronization signal S_(v1). The DC/AC converter 4 can be implemented like a conventional DC/AC converter that is configured to generate an output current in phase with an alternating reference signal. Such DC/AC converters are commonly known.

It should be noted that each of the DC/AC converter units 2 ₁, 2 ₂, 2 _(n) controls its output current i1 to have a phase and frequency that is dependent on the at least one synchronization signal S_(v1).

The reference signal S_(REF) is generated by a control circuit 5 dependent on the synchronization signal S_(v1) and an output current signal S_(i1). The synchronization signal S_(v1) is either the synchronization signal S_(v1) explained with reference to FIG. 1, one of the measurement voltages v1 _(i) explained with reference to FIG. 3, or a scaled version or a fraction thereof. The output current signal S_(i1) represents the output current i1, i.e., the output current signal S_(i1) is dependent on the output current i1. According to one embodiment, the output current signal S_(i1) is a scaled version of the output current i1. The output current signal S_(i1) can be generated in a conventional manner from the output current i1 using a current measurement circuit (not illustrated). The output current signal S_(i1) is generated for each of the converter units (2 ₁-2 _(n)) individually by detecting the respective output current of each converter unit. Referring to FIG. 5, the output current i1 of the illustrated converter unit 2 is the current received at the circuit node common to the first output terminal 23 and the output capacitance C.

The control circuit 5, which will also be referred to as controller in the following, generates the reference signal S_(REF) dependent on the synchronization signal S_(v1) and the output current signal S_(i1) such that the output current, when generated in correspondence with the reference signal S_(REF), is in phase with the external AC voltage v1 or has a given phase shift relative to the external AC voltage v1. It should be noted that, since the external AC voltage v1 and the output current i1 are alternating signals, the synchronization signal S_(v1) and the output current signal S_(i1) are also alternating signals. In the converter unit 2, the DC/AC converter 4 and the controller 5 are part of a control loop that controls the output current i1 to be in phase with the external AC voltage v1 or to have a given phase shift relative thereto.

Although a conventional DC/AC converter may be used in the converter unit 2 as the DC/AC converter 4 connected between the input terminals 21, 22 and the output terminals 23, 24, one example of a DC/AC converter 4 will be explained in detail with reference to FIG. 6, in order to ease understanding of embodiments of the invention.

The DC/AC converter 4 illustrated in FIG. 6 is a full-bridge (H4) converter with two half-bridge circuits each connected between the input terminals 21, 22. Each of these half-bridge circuits includes two switches each having a load path and a control terminal. The load paths of the two switches of one half-bridge circuit are connected in series between the input terminals 21, 22, where a first switch 42 ₁ and a second switch 42 ₂ form the first half-bridge, and a third switch 42 ₃ and a fourth switch 42 ₄ form the second half-bridge. Each of the half-bridges includes an output, where an output of the first half-bridge is formed by a circuit node common to the load paths of the first and second switch 42 ₁, 42 ₂. An output of the second half-bridge is formed by a circuit node common to the load paths of the third and fourth switches 42 ₂, 42 ₄. The output of the first half-bridge is coupled to the first output terminal 23 of the converter unit 2 via a first inductive element 44 ₁, such as a choke. The output terminal of the second half-bridge is coupled to the second output terminal 24 of the converter unit 2 via a second inductive element 44 ₂, such as a choke. According to a further embodiment (not illustrated) only one of the first and second inductive elements 44 ₁, 44 ₂ is employed. The converter 4 further includes an input capacitance 41, such as a capacitance, connected between the input terminals 21, 22, and the output capacitance C connected between the output terminals 23, 24.

Each of the switches 42 ₁, 42 ₂, 42 ₃, 42 ₄ receives a control signal S42 ₁, S42 ₂, S42 ₃, S42 ₄ at its control terminal. These control signals S42 ₁-S42 ₄ are provided by a drive circuit 45 dependent on the reference signals S_(REF) received from the controller 5. The drive signal S42 ₁-S42 ₄ are pulse-width modulated (PWM) drive signals configured to switch the corresponding switch 42 ₁-42 ₄ on and off. It should be noted that a switching frequency of the PWM signals S42 ₁-S42 ₄ is significantly higher than a frequency of the alternating reference signal S_(REF). The reference signal S_(REF) may be a sinusoidal signal with a frequency of 50 Hz or 60 Hz, depending on the country in which the power grid is implemented, while the switching frequency of the individual switches 42 ₁-42 ₄ may be in the range of several kHz up to several 10 kHz, or even up to several 100 kHz. The drive circuit 45 is configured to individually adjust the duty cycle of each of the drive signals S42 ₁-S42 ₄ between 0 and 1 in order to have the waveform of the output current i1 follow the waveform of the reference signal S_(REF). When the duty cycle of one drive signal is 0, the corresponding switch is permanently switched off, and when the duty cycle of one drive signal is 1, the corresponding switch is permanently switched on. The duty cycle of a drive signal is the relationship between the time period for which the drive signal switches the corresponding switch and the duration of one switching cycle. The duration of one switching cycle is the reciprocal of the switching frequency.

Referring to what has been explained before, the output current i1 is an AC current with a positive half-cycle in which the output current is positive, and with a negative half-cycle in which the output current i1 is negative. The time behavior of the output current i1 is dependent on the reference signal S_(REF) which also has positive and negative half-cycles.

Two possible operating principles of the converter 4 will briefly be explained. First, it is assumed that a positive half-cycle of the output current i1 is to be generated. According to a first operating principle, which is known as bipolar switching or 2-level switching, the first and fourth switches 42 ₁, 42 ₄ are switched on and off synchronously, while the second and third switches 42 ₂, 42 ₃ are permanently switched off. During an on-phase of the first and fourth switches 42 ₁, 42 ₄ an output current i1 is forced through the choke(s) 44 ₁, 44 ₂ that is dependent on the voltage difference between the input voltage V3 across the input capacitance 41 and the output voltage v2, where the output voltage v2 is defined by the power grid voltage v_(N). The switches 42 ₁-42 ₄ each include a freewheeling element, such as a diode, that is also illustrated in FIG. 4. The freewheeling elements of the second and third switches 42 ₂, 42 ₃ take the current flowing through the choke(s) 44 ₁, 44 ₂ when the first and fourth switches 42 ₁, 42 ₄ are switched off. In this method, the amplitude of the output current i1 can be adjusted through the duty cycle of the synchronous switching operation of the first and fourth switches 42 ₁, 42 ₄. When the switching frequency of the switches 42 ₁, 42 ₄ is much higher than the desired frequency of the output current, amplitude, frequency and phase of the AC output current i1 can be adjusted dependent on the reference signal S_(REF) through the duty cycle of the synchronous switching operation of the first and fourth switches 42 ₁, 42 ₄. During the negative half-cycle the second and third switches 42 ₂, 42 ₃ are switched on and off synchronously, while the first and fourth switches 42 ₁, 42 ₄ are permanently off, so that the body diodes of these first and fourth switches 42 ₁, 42 ₄ are conducting. Alternatively, the switches 42 ₁, 42 ₄ are switched (with short dead times) when their body diodes are forward biased, so as to be operated as synchronous rectifiers.

According to a second operating principle, which is known as phase chopping or 3-level switching, the first switch 42 ₁ is permanently switched on during the positive half cycle of the output voltage v2, the second and third switches 42 ₂, 42 ₃ are permanently off, and the fourth switch 42 ₄ is switched on and off in a clocked fashion. During an on-phase of the first and fourth switches 42 ₁, 42 ₄ an output current i1 is forced through the choke(s) 44 ₁, 44 ₂ that is dependent on voltage difference between the input voltage V3 across the input capacitance 41 and the output voltage v2, where the output voltage v2 is defined by the power grid voltage v_(N). During an off-phase of the fourth switch 42 ₄ a freewheeling path is offered by the freewheeling element of switch 42 ₃ and the switched-on first switch 42 ₁ thus enabling a zero volt state across the output chokes. In this method, the amplitude of the output current i1 can be adjusted through the duty cycle of the switching operation of the fourth switch 42 ₁, 42 ₄. During the negative half-cycle the first and fourth switches 42 ₁, 42 ₄ are permanently switched off, the second switch 42 ₂ is permanently switched on, and the third switch 42 ₃ is switched on and off in a clocked fashion.

In order to control an instantaneous amplitude of the output current i1 during the positive half-cycle, the drive circuit 45 varies the duty cycle of the at least one switch that is switched on and off in a clocked fashion. The duty cycle of the at least one clocked switch and the duty cycle of its drive signal, respectively, is increased in order to increase the amplitude of the output current i1 and is decreased in order to decrease the amplitude of the output current i1. This duty cycle is dependent on the instantaneous amplitude of the reference signal S_(REF).

The switches 42 ₁-42 ₄ may be implemented as conventional electronic switches. Referring to FIG. 7A, which illustrates a first embodiment for implementing the switches, the switches may be implemented as MOSFETs, specifically as n-type MOSFETs. Electronic switch 42 in FIG. 7A represents an arbitrary one of the switches 42 ₁-42 ₄. A MOSFET, such as the n-type MOSFET illustrated in FIG. 7A has an integrated diode that is also illustrated in FIG. 7A. This diode is known as body diode and may act as a freewheeling element. A drain-source path, which is a path between a drain terminal and a source terminal, forms a load path of a MOSFET, and a gate terminal forms a control terminal.

Referring to FIG. 7B, the switches 42 ₁-42 ₄ could also be implemented as IGBTs, where additionally a diode may be connected between a collector and an emitter terminal of the IGBT. This diode acts as a freewheeling element. In an IGBT, the load path runs between the emitter and the collector terminal, and the gate terminal forms a control terminal.

According to a further embodiment, two of the four switches, such as the first and third transistors 42 ₁, 42 ₃ are implemented as SCR Thyristors, while the other two switches are implemented as MOSFET.

According to yet another embodiment, illustrated in FIG. 7C, the switches 42 ₁-42 ₄ can be implemented as GaN-HEMTs (Gallium-Nitride High Electron Mobility Transistors). Unlike a conventional (silicon or silicon carbide) MOSFET a GaN-HEMT does not include an integrated body diode. In a GaN-HEMT, a current conduction in a reverse direction (corresponding to the forward direction of a body diode in a conventional MOSFET) can be obtained through a substrate biased turn-on. When implementing the switches in GaN technology, all switches of one converter unit can be implemented on a common semiconductor substrate.

FIG. 8 schematically illustrates an embodiment of the controller 5 that generates the reference signal S_(REF) dependent on the synchronization signal S_(V1) and the output current signal S_(i1). FIG. 8 shows a block diagram of the controller 5 in order to illustrate its operating principle. It should be noted that the block diagram illustrated in FIG. 8 merely serves to illustrate the functionality of the controller 5 rather than its implementation. The individual function blocks, that will be explained in further detail below, may be implemented using a conventional technology that is suitable to implement a controller. Specifically, the function blocks of the controller 5 may be implemented as analog circuits, digital circuits, or may be implemented using hardware and software, such as a microcontroller on which a specific software is running in order to implement the functionality of the controller 5.

Referring to FIG. 8, the controller 5 includes a phase locked loop (PLL) 51 that provides a frequency and phase signal S_(ωt) representing the frequency and the phase of the synchronization signal S_(v1). Specifically, S_(ωt) represents an instantaneous phase angle of the (sinusoidal) synchronization signal received at the input of the control circuit 5. Thus, signal S_(ωt) will also be referred to as phase angle signal in the following. The PLL 51 receives the synchronization signal S_(v1). The frequency and phase signal S_(ωt) provided by the PLL 51 is received by a signal generator, such as a VCO, that generates a sinusoidal signal S_(i1-REF) being in phase with the synchronization signal S_(v1) and forming a reference signal for the output current i1 of the converter unit 2.

Referring to FIG. 8, the controller further receives the output current signal S_(i1) and calculates an error signal by subtracting the output current signal S_(i1) from the output current reference signal S_(i1-REF). The subtraction operation is performed by a subtractor receiving the output current measurement signal S_(i1-REF) and the output current signal S_(i1) at input terminals and providing the error signal at an output terminal. The error signal, which is also a sinusoidal signal is filtered in a filter 53 connected downstream the subtractor 54. The reference signal S_(REF) is a filtered version of the error signal available at the output of the filter 53. The filter is, e.g., a proportional (P) filter.

Optionally, a phase signal S_(φ) is added to the output signal of the PLL 51 before generating the sinusoidal reference signal S_(i1-REF). In this embodiment the reference signal S_(i1-REF) and, therefore, the output current i1, has a phase relative to the synchronization signal S_(v1), with the phase shift being defined by the phase signal S_(φ).

FIG. 9 illustrates an embodiment of the PLL 51 of FIG. 6. This PLL includes a phase detector with a calculation unit 511 that calculates the sine or the cosine of the phase angle signal S_(ωt), and multiplier 512 that receives the output signal from the calculation unit 511 and the synchronization signal S_(v1). An error signal S_(ERROR) is available at the output of the multiplier 512. The error signal S_(ERROR) is received by a linear filter (LF) 514, such as, e.g., a linear proportional-integral (PI) filter. In the steady state, an output signal S_(ω) of the linear filter represents the frequency of the synchronization signal S_(v1). An integrating circuit (a filter with an integrating (I) characteristic) receives the output signal from the linear filter, integrates the output signal of the linear filter 514 and provides the frequency and phase signal (the phase angle signal) S_(ωt), from which the VCO (see 52 in FIG. 8) generates the reference signal S_(i1-REF). Integrating the output signal of the linear filter in the time domain corresponds to a multiplication with 1/s in the frequency domain.

FIG. 10 illustrates a further embodiment of the of the controller 5. In this embodiment, a second PLL 51′ receives the output current signal S_(i1) and calculates a further frequency and phase signal representing frequency and phase of the output current signal S_(i1). The further frequency and phase signal is subtracted from the frequency and phase signal S_(ωt) representing frequency and phase of the synchronization signal S_(v1) (and, optionally, the phase shift Sφ) using a subtractor 54, so as to provide an error signal. The error signal is filtered using a filter 53 and a signal generator 52, such as a VCO, receives the error signal and generates a sinusoidal reference signal with frequency and phase defined by the filtered error signal. In this embodiment, the filter 53 can be implemented as a P-filter or as a PI-filter.

FIG. 11 illustrates a further embodiment of one converter unit 2. This converter unit besides the DC/AC converter 4 and the controller 5 includes a DC/DC converter 6 connected between the input terminals 21, 22, and the DC/AC converter 4. The DC/AC converter 4 may be implemented as explained with reference to FIGS. 6 to 10 with the difference that the DC/AC converter 4 of FIG. 11 receives a DC input voltage V6 from the DC/DC converter 6 instead of the input voltage V3 of the converter unit 2. A capacitor 60 connected between the terminals 61, 62 may represent an output capacitor of the DC/DC converter 6 or an input capacitor 4 of the DC/AC converter 4, or both. This capacitor 60 can be referred to as DC link capacitor.

The DC/DC converter 6 is configured to adjust the input voltage V3 or the input current I3 to a voltage or current value, respectively, that is dependent on a reference signal S_(REF-V3) received by the DC/DC converter 6. For explanation purposes it is assumed that the DC/DC converter 6 adjusts the input voltage V3 dependent on the reference signal S_(REF-V3). Adjusting the input voltage V3 of the converter unit 2 may help to operate the DC power source 3 connected to the input terminals 21, 22, in an optimum operating point. This will be explained in the following.

A solar cell and, therefore, a PV module including several solar cells, acts like a power generator providing a DC output voltage and a DC output current when it is exposed to sunlight. For a given light power received by the PV array there is a range of output currents and a range of corresponding output voltages at which the PV array can be operated. However, there is only one output current and one corresponding output voltage at which the electric power provided by the PV array has its maximum. The output current and the output voltage at which the output power assumes its maximum define the maximum power point (MPP). The MPP varies dependent on the light power received by the array and dependent on the temperature.

Referring to FIG. 11, the converter unit 2 further includes a maximum power point tracker (MPPT) 7 that is configured to provide the reference signal S_(REF-V3) such that DC/DC converter 6 adjusts the input voltage such that the DC source 3 is operated in its MPP. The MPPT 7 receives an input current signal S_(I3) that represents the input current I3 provided by the DC source 3 (illustrated in dashed lines in FIG. 9), and an input voltage signal S_(V3) that represents the input voltage V3 provided by the DC source 3. From the input current signal S_(I3) and the input voltage signal S_(V3) the MPPT 7 calculates the instantaneous input power provided by the DC source 3. The input voltage signal S_(V3) can be obtained from the input voltage V3 in a conventional manner by, for example, using a voltage measurement circuit. Equivalently, the input current signal S_(I3) can be obtained from the input current I3 in a conventional manner using, for example, a current measurement circuit. Those voltage measurement circuits and current measurement circuits are commonly known and are not illustrated in FIG. 11.

The basic operating principle of the MPPT 7 in order to find the MPP is to vary the reference signal S_(REF-V3) within a given signal range and to determine the input power provided by the DC source 3 for each of the input voltages V3 defined by the different reference signals S_(REF-V3). The MPPT 7 is further configured to detect the input voltage V3 for which the maximum input power has been obtained, and to finally set the reference signal S_(REF-V3) to that value for which the maximum input power has been detected.

Since the solar energy received by the PV array 3 may vary the MPPT 7 is further configured to check whether the DC source 3 is still operated in its maximum power point either regularly or when there is an indication that the maximum power point might have changed. An indication that the maximum power point might have changed is, for example, when the input current I3 represented by the input current signal S_(I3) changes without the reference signal S_(REF-V3) having changed. The regular check or the event-driven check of the MPPT 7 whether the DC source 3 is still operated in its maximum power point, may include the same algorithm that has been explained before for detecting the maximum power point for the first time. Conventional algorithms for detecting the maximum power point that can be implemented in the MPPT 7 include, for example, a “hill climbing algorithm” or a “perturb-and-observe algorithm.”

The DC/DC converter 6 can be implemented like a conventional DC/DC converter. A first embodiment of a DC/DC converter 6 that can be used in the converter unit 2 is illustrated in FIG. 12. The DC/DC converter 6 illustrated in FIG. 12 is implemented as a boost converter. This type of converter includes a series circuit with an inductive storage element 64, such as a choke, and a switch 65 between the input terminals of the DC/DC converter 6, where the input terminals of the DC/DC converter 6 correspond to the input terminals 21, 22 of the converter unit 2. Further, a rectifier element 66, such as a diode, is connected between a circuit node common to the inductive storage element 64 and the switch 65 and a first output terminal 61 of the DC/DC converter 6. A second output terminal 62 of the DC/DC converter 6 is connected to the second input terminal 22. An output voltage V6 of the DC/DC converter is available between the output terminals 61, 62. Referring to FIG. 12, the DC/DC converter 6 may further include a first capacitive storage element 63, such as a capacitor, between the input terminals 21, 22, and a second capacitive storage element 68, such as a capacitor, between the output terminals 61, 62. The second capacitive storage element 68 acts as an energy storage that is necessary when generating the AC output current i1 from the DC voltage V6 available at the output of the DC/DC converter 6.

The switch 65 can be implemented as a conventional electronic switch, such as a MOSFET or an IGBT. Further, the rectifying element 66 could be implemented as a synchronous rectifier, which is a rectifier implemented using an electronic switch, such as a MOSFET or an IGBT. According to a further embodiment, the switch 65 is implemented as GaN-HEMT.

The DC/DC converter 6 further includes a control circuit (controller) 67 for generating a drive signal S65 for the switch 65. This drive signal S65 is a pulse-width modulated (PWM) drive signal. The PWM controller 67 is configured to adjust the duty cycle of this drive signal S65 such that the input voltage V3 corresponds to the desired input voltage as represented by the reference signal S_(REF-V3). For this, the control circuit 67 receives the reference signal S_(REF-V3) and the input voltage signal S_(V3) that represents the input voltage V3.

A first embodiment of the PWM control circuit 67 is illustrated in FIG. 13. Like in FIG. 8 (which illustrates an embodiment of the controller 5) in FIG. 11 functional blocks of the controller 67 are illustrated. These functional blocks can be implemented as analog circuits, as digital circuits or can be implemented using hardware and software. Referring to FIG. 13, the control circuit 67 calculates an error signal S_(ERR) from the input voltage signal S_(V3) and the reference signal S_(REF-V3). The error signal S_(ERR) is calculated by either subtracting the input voltage signal V3 from the reference signal S_(REF-V3) (as illustrated) or by subtracting the reference signal S_(REF-V3) from the input voltage signal S_(V3). The error signal S_(ERR) is provided by a subtraction element 671 that receives the input voltage signal S_(V3) and the reference signal S_(REF-V3).

The error signal S_(ERR) is received by a filter 672 that generates a duty cycle signal S_(DC) from the error signal S_(ERR). The duty cycle signal S_(DC) represents the duty cycle of the drive signal S65 provided by the control circuit 67. The filter 672 can be a conventional filter for generating a duty cycle signal S_(DC) from an error signal S_(ERR) in a PWM controller of a DC/DC converter, such as a P-filter, a PI-filter, or a PID-filter.

A PWM driver 673 receives the duty cycle signal S_(DC) and a clock signal CLK and generates the drive signal S65 as a PWM signal having a switching frequency as defined by the clock signal CLK and a duty cycle as defined by the duty cycle signal S_(DC). This driver 673 can be a conventional PWM driver that is configured to generate a PWM drive signal based on a clock signal and a duty cycle information. Such drivers are commonly known, so that no further information are required in this regard.

The basic control principle of the controller 67 of FIG. 12 will briefly be explained. Assume that the input voltage V3 has been adjusted to a given value represented by the reference signal S_(REF-V3) and that the reference signal S_(REF-V3) changes, so that the input voltage V3 has to be re-adjusted. For explanation purposes it is assumed that the input voltage V3 is to be increased as defined by the reference signal S_(REF-V3). In this case the control circuit 67 reduces the duty cycle of the drive signal S65. Reducing the duty cycle of the drive signal S65 results in a decreasing (average) input current I3, where decreasing the input current I3, at a given power provided by the DC source 3 results in an increasing input voltage V3. Equivalently, the duty cycle is increased when the input voltage V3 is to be decreased. An increase in the duty cycle results in an increase of the input current I3.

The boost converter according to FIG. 12 does not only provide a load to the DC source 3 in order to operate the DC source 3 in its maximum power point. This boost converter also generates an output voltage V6 received by the DC/AC converter 4 (see FIG. 11) that his higher than the input voltage V3. Further, the boost converter is implemented such that the output voltage V6 is higher than a peak voltage of the output voltage v2 of the DC/AC converter, but lower than a voltage blocking capability of the switches (see 42 ₁-42 ₄ in FIG. 6) implemented in the DC/AC converter.

Referring to FIG. 14, the DC/DC converter 6 may also be implemented as a buck converter. This buck converter includes a series circuit with an inductive storage element 64, such as a choke, and a switch 65 between the first input terminal 21 and the first output terminal 61. A freewheeling element 66, such as a diode, is connected between the second output terminal 62 and a circuit node common to the inductive storage element 64 and the switch 65. A capacitive storage element 63, such as a capacitor, is connected between the input terminals 21, 22.

Like in the boost converter of FIG. 12, the switch 65 in the buck converter of FIG. 14 can be implemented as a conventional electronic switch, such as a MOSFET or an IGBT, or could be implemented as a GaN-HEMT. Further, the freewheeling element 66 could be implemented as a synchronous rectifier.

Like in the boost converter according to FIG. 12, the switch 65 in the buck converter according to FIG. 14 is driven by a PWM drive signal S65 provided by a control circuit 67. The control circuit 67 may be implemented as illustrated in FIG. 13. The operating principle of the control circuit 67 in the buck converter of FIG. 14 is the same as in the boost converter of FIG. 12, i.e., the duty cycle of the drive signal S65 is increased when the input voltage V3 is to be decreased, and the duty cycle is decreased, when the input voltage V3 is to be increased.

It should be noted that implementing the DC/DC converter 6 as a boost converter (see FIG. 12) or as a buck converter (see FIG. 14) is only an example. The DC/DC converter 6 could also be implemented as a buck-boost converter, a boost-buck-converter, a flyback converter, and so on. Whether a boost converter or a buck converter is used as a DC/DC converter for tracking the maximum power point of the DC source 3 and for providing the input voltage V6 to the DC/AC converter 4, influences the number of converter units 2 to be connected in series in order for the sum of the output voltages v2 of the converter units 2 to correspond to the external AC voltage v1. This will be explained by the way of an example in the following.

Assume that there is an external AC voltage v1 with 240V_(RMS) is desired. The peak voltage (maximum amplitude) of this voltage v1 is 338V (240V·sqrt(2), where sqrt is the square root). Further assume that the DC sources 3 are PV arrays each providing an output voltage between 24V and 28V when exposed to sunlight. The DC/AC converter 4 has a buck characteristic, which means that the peak value of the output voltage v2 (see FIG. 4) is less than the received DC input voltage V3 or V6, respectively. Thus, when buck converters are employed as DC/DC converters 6 in the converter units 2 or when no DC/DC converters are used, at least 15 converter units 2 with PV panels connected thereto need to be connected in series. This is based on the assumption that each PV array generates a minimum voltage of V3=24V and that a peak voltage of the external AC voltage v1 is 338V. The number of 15 is obtained by simply dividing 338V through 24V (338V/24V=14.08) and rounding the result to the next higher integer.

When, however, a boost converter is used as the DC/DC converter 6 that, for example, generates an output voltage V6=60V from the input voltage V3 (which is between 24V and 28V) the number of converter units 2 to be connected in series may be reduced to about 6.

In the DC/AC converter illustrated in FIG. 11, the output voltage V6 of the DC/DC converter may vary dependent on the input power received at the input terminals 21, 22 from the DC source 3 and dependent on the output current i1 or, more exactly, dependent on the average of the output current i1. According to a further embodiment illustrated in FIG. 15, the control circuit 5 is further configured to control the input voltage of the DC/AC converter 4 and the output voltage of the DC/DC converter 6, respectively. For this, the control circuit 5 receives an input voltage signal S_(V6) that represents the input voltage V6. The control circuit 5 is configured to adjust the input voltage V6 by varying the duty cycle of those switches in the DC/AC converter 4 that are driven in a clocked fashion. The input voltage can be increased by generally decreasing the duty cycle and can be decreased by generally increasing the duty cycle. For this, the control circuit 5 includes a further control loop, where this control loop is slower than the control loop that causes the output current i1 to follow the reference signal S_(REF). This control loop is, for example configured to cause variations of the duty cycle at a frequency of between 1 Hz and 10 Hz.

The control circuit 5 of FIG. 15 is based on the control circuit illustrated in FIG. 8 and additionally includes a further control loop that serves to adjust the amplitude of the output current reference signal S_(i1-REF) dependent on the input voltage signal S_(V6). Instead of the control loop illustrated in FIG. 8, the control circuit according to FIG. 15 could also be implemented based on the control circuit of FIG. 10. Referring to FIG. 15, the control loop includes: a further subtraction element 56, a filter 55, and a multiplier 57. The subtraction element 56 receives the input voltage signal S_(V6) and a reference signal S_(V6-REF) that represents a set value of the input voltage V6. The subtraction element 56 generates a further error signal based on a difference between the input voltage signal S_(V6) and the reference signal S_(V6-REF). The filter 55 receives the further error signal and generates an amplitude signal S_(AMPL) representing an amplitude of the reference signal S_(REF) from the further error signal. The filter may have a P-characteristic, an I-characteristic, a PI-characteristic, or a PID-characteristic. The amplitude signal S_(AMPL) and the output signal of the VCO 52 are received by the multiplier 57 that provides the output current reference signal S_(i1-REF). The output current reference signal S_(i1-REF) has an amplitude that is dependent on the input voltage V6 and that serves to control the input voltage V6 of the DC/AC converter (4 in FIG. 11), and a frequency and phase of the output current i1. The frequency and the phase of the reference signal S_(REF) are dependent on the at least one synchronization signal S_(v1) and the output current signal S_(i1) and serve to adjust frequency and phase of the output current i1 such that there is a given phase difference between the output current and the output voltage.

The input voltage reference signal S_(V6-REF) may have a fixed value that is, selected such that the input voltage V6 is sufficiently below the voltage blocking capability of switches employed in the DC/AC converter. However, it is also possible to vary the input voltage reference signal S_(V6-REF) dependent on the output current, specifically on the rms value of the output current i1. According to one embodiment, the input voltage reference signal S_(V6-REF) decreases when the output current i1 increases, and the input voltage reference signal S_(V6-REF) increases when the output current decreases. According to one embodiment, the input voltage reference signal S_(V6-REF) has a first signal value when the output current i1 is below a given threshold value, and has a lower second signal value when the output current i1 is above a given threshold value.

The control circuit illustrated in FIG. 15 could also be implemented in a converter as illustrated in FIG. 6 in which the DC/DC converter is omitted. In this case, the input voltage to be controlled is the output voltage V3 of the PV module, so that the voltage signal S_(V6) in FIG. 15 is replaced by the voltage signal S_(V3) representing the output voltage of the DC source 3, and the input voltage reference signal S_(V6-REF) is replaced by the reference signal S_(V3-REF) defining a desired output voltage of the DC source 3. The input voltage reference signal S_(V3-REF) may in this case be provided by an MPPT in order to operate the DC source (PV module) 3 in its MPP.

FIG. 16 illustrates a further embodiment of DC/DC converter 6 that can be implemented in a DC/AC converter unit 2 of FIG. 11. The DC/DC converter of FIG. 16 is implemented as a boost converter with two converter stages 60 ₁, 60 ₂. The two converter stages 60 ₁, 60 ₂ are connected in parallel between the input terminals 21, 22 and the output terminals 61, 62. Each of the converter units 60 ₁, 60 ₂ is implemented like the boost converter of FIG. 12 and includes a series circuit with an inductive storage element 64 ₁, 64 ₂, such as a choke, and a switch 65 ₁, 65 ₂ between the input terminals of the DC/DC converter 6, where the input terminals of the DC/DC converter 6 correspond to the input terminals 21, 22 of the converter unit 2. Further, each converter stage includes a rectifier element 66 ₁, 66 ₂ such as a diode, connected between a circuit node common to the corresponding inductive storage element 64 ₁, 64 ₂ and the corresponding switch 65 ₁, 65 ₂ and the first output terminal 61 of the DC/DC converter 6. The second output terminal 62 of the DC/DC converter 6 is connected to the second input terminal 22.

The two converter stages 60 ₁, 60 ₂ share the first capacitive storage element 63 between the input terminals 21, 22, and share the second capacitive storage element 68 between the output terminals 61, 62. The output voltage V6 of the DC/DC converter 6 is available across the second capacitive storage element 68.

Referring to FIG. 16, the control circuit (controller) 67 of the DC/DC converter 6 generates two PWM drive signals S65 ₁, S65 ₂, namely a first drive signal S65 ₁ for the switch 65 ₁ of the first converter stage 60 ₁, and a second drive signal S65 ₂ for the switch 65 ₂ of the second converter stage 60 ₂. According to one embodiment, the first and second boost converter stages 60 ₁, 60 ₂ are operated interleaved, which means that there is a time offset between the switching cycles of the first switch 65 ₁ and the switching cycles of the second switch 65 ₂. Providing two converter stages 60 ₁, 60 ₂ and operating these converter stages 60 ₁, 60 ₂ in an interleaved mode helps to reduce voltage ripples of the input voltage V3 and the output voltage V6 of the DC/DC converter 6. Of course, more than two boost converter stages 60 ₁, 60 ₂ can be connected in parallel.

Referring to FIG. 16, each boost converter stage 60 ₁, 60 ₂ provides an output current I6 ₁, I6 ₂. These output currents I6 ₁, I6 ₂ add and form the overall output current I6 of the DC/DC converter. FIG. 17 illustrates a first embodiment of the controller 67 configured to generate PWM drive signals S65 ₁, S65 ₂ for each converter stage 60 ₁, 60 ₂, and further configured to generate the PWM drive signals S65 ₁, S65 ₂ such that the output currents I6 ₁, I6 ₂ of the converter stages 60 ₁, 60 ₂ are balanced.

Referring to FIG. 17 the control circuit 67 is based on the control circuit 67 of FIG. 13 and includes the subtraction element 671 receiving the input voltage signal S_(V3) and the input voltage reference signal S_(REF-V3) and the filter 672 for providing the duty cycle signal S_(DC). The controller 67 of FIG. 17 further includes a first PWM driver 673 ₁ receiving a first duty cycle signal S_(DC1) that is dependent on the duty cycle signal S_(DC) provided by the filter 672 and receiving a first clock signal CLK₁, and a second PWM driver 673 ₁ receiving a second duty-cycle signal S_(DC2) that is dependent on the duty cycle signal S_(DC) provided by the filter 672 and receiving a second clock signal CLK₂. According to one embodiment, the first and second clock signals CLK₁, CLK₂ have the same frequency. However, there is a phase shift between the first and second clock signal CLK₁, CLK₂, so that there is a phase shift between the first PWM drive signal S65 ₁ provided by the first PWM driver 673 ₁ and the second PWM drive signal S65 ₂ provided by the second PWM driver 673 ₂.

If the first and second converter stages 60 ₁, 60 ₂ would perfectly match so that there would be no risk of unbalanced output currents I6 ₁, I6 ₂, the duty cycle signal S_(DC) could be used as the first duty cycle signal S_(DC1) and as the second duty cycle signal S_(DC2). However, due to an inevitable mismatch of the components in the converter stages 60 ₁, 60 ₂ the output currents I6 ₁, I6 ₂ can be unbalanced when the first and second drive signal S65 ₁, S65 ₂ would be generated with exactly the same duty cycle.

In order to compensate for such unbalances of the first and second output currents I6 ₁, I6 ₂, the controller 67 of FIG. 17 includes an additional control loop, that can be referred to as current balancing loop or power balancing loop. This control loop receives a first output current signal S_(I61) representing the first output current I6 ₁ of the first converter stage 60 ₁, and a second output current signal S_(I62) representing the output current I6 ₂ of the second converter stage 60 ₂. These output current signals S_(I61), S_(I62) can be generated using conventional current measurement units. The output current signals S_(I61), S_(I62) are received by a subtraction unit 675 that generates a further error signal S_(ERR2). The further error signal S_(ERR2) is representative of a difference between the first and second output currents I6 ₁, I6 ₂. Further error signal S_(ERR2) is received by a filter 676 that generates a filtered error signal. The filter 676 may have a P-characteristic, an I-characteristic, or a PI-characteristic.

A further subtraction unit 674 ₁ subtracts the filtered error signal from the duty cycle signal S_(DC) to generate the first duty cycle signal S_(DC1), and an adder 674 ₂ adds the filtered error signal to the duty cycle signal DC to generate the second duty cycle signal S_(DC2).

The operating principle of the controller 67 of FIG. 17 is as follows. When the first and second output currents I6 ₁, I6 ₂ are identical, the further error signal S_(ERR2) is zero. In this case, the first duty cycle signal S_(DC1) corresponds to the second duty cycle signal S_(DC2). When, for example, the first output current I6 ₁ is larger than the second output current I6 ₂, the further error S_(ERR2) and the filtered error signal have a positive value. In this case, the duty cycle signal S_(DC1) (obtained by subtracting the filtered error signal from the duty cycle signal S_(DC)) becomes smaller than the second duty cycle signal S_(DC2) (obtained by adding the filtered error signal to the duty cycle signal S_(DC)). Thus, the duty cycle of the first drive signal S65 ₁ becomes smaller than the duty cycle of the second drive signal S65 ₂ in order to reduce the first output current I6 ₁ and to increase the second output current I6 ₂, so as to balance these output currents I6 ₁, I6 ₂.

FIG. 18 illustrates a further embodiment of the control circuit 67 that is configured to balance the output currents I6 ₁, I6 ₂. The control circuit 67 of FIG. 18 is based on the control circuit 67 of FIG. 17. In the control circuit 67 of FIG. 18, the subtraction unit 674 ₁ that generates the first duty cycle signal S_(DC1) does not receive the duty cycle signal S_(DC) but receives a filtered version of a difference between the duty cycle signal S_(DC) and the first output current signal S_(I61). A subtraction unit 677 ₁ calculates the difference and a filter 678 ₁, filters the difference. The filter may have a P-characteristic, an I-characteristic or PI-characteristic. Equivalently, the adder 674 ₂ that provides the second duty cycle signal S_(DC2) does not receive the duty cycle signal S_(DC) but receives a filtered difference between the duty cycle signal S_(DC) and the second input current signal S_(I62). A subtraction unit 677 ₂ calculates the difference between the duty cycle signal S_(DC) and the second output current signal S_(I62), and a filter 678 ₂ filters the difference. The output signals of the filter 678 ₁, 678 ₂ are received by the subtraction unit 674 ₁ and the adder 674 ₂, respectively.

While in the embodiment illustrated in FIG. 17 a single control loop is employed to regulate the input voltage V3, a dual control loop structure is employed in the embodiment according to FIG. 18.

FIG. 19 illustrates a further embodiment of a converter unit 2 with a DC/AC converter 4. The converter unit 2 may further include a DC/DC converter 6 (see FIG. 9) connected between the input terminals 21, 22 and the DC/AC converter. However, such DC/DC converter is not illustrated in FIG. 13. Dependent on whether or not the converter unit 2 includes a DC/DC converter the DC/AC converter 4 receives the input voltage V3 of the converter unit 2 or the output voltage of the DC/DC converter 4 (not illustrated in FIG. 19) as an input voltage. For explanation purposes, it is assumed that the DC/AC converter 4 receives the input voltage V3.

The DC/AC converter of FIG. 19 includes a buck converter 80 that receives the input voltage V3 as an input voltage. The buck converter 80 is configured to generate an output current i80 which is a rectified version of the output current i1 of the DC/AC converter 4. Assume, for example that a desired waveform of the output current i1 is a sinusoidal waveform. In this case, the output current i80 provided by the converter 80 has the waveform of a rectified sinusoidal curve or the waveform of the absolute value of a sinusoidal curve, respectively. This is schematically illustrated in FIG. 20, in which exemplary timing diagrams of a sinusoidal output current i1 and the corresponding output current i80 of the converter 80 are illustrated.

The output current i1 of the DC/AC converter 4 is produced from the output current i80 of the buck converter 80 using a bridge circuit 85 with two half-bridges, where each of these half-bridges is connected between output terminals 81, 82 of the buck converter 80. This bridge circuit 85 can be referred to as unfolding bridge. A first half-bridge includes a first and a second switch 85 ₁, 85 ₂ connected in series between the output terminals 81, 82, and a second half-bridge includes a third switch 85 ₃ and a fourth switch 85 ₄ connected in series between the output terminals 81, 82. An output terminal of the first half-bridge, which is a circuit node common to the first and second switches 85 ₁, 85 ₂ is coupled to the first output terminal 23. An output terminal of the second half-bridge, which is a circuit node common to the third and fourth switch 85 ₃, 85 ₄ is coupled to the second output terminal 24 of the converter unit 2. Optionally, an EMI filter 88 with two inductances, such as chokes, is coupled between the output terminals of the half-bridges and the output terminals 23, 24 of the converter unit 2. The output capacitance C of the converter unit 2 that is connected between the output terminals can be part of the EMI filter 88.

Referring to FIG. 19, the output current i80 of the buck converter 80 has a frequency which is twice the frequency of the output current i1. A switching frequency of the switches 85 ₁-85 ₄ of the bridge circuit 85 corresponds to the frequency of the output current i1. During a positive half-cycle of the output current i1 the first and fourth switch 85 ₁, 85 ₄ are switched on, and during a negative half-cycle of the output voltage v2 the second and third switches 85 ₂, 85 ₃ are switched on. The switches of the bridge circuit 85 are driven by drive signals S85 ₁-S85 ₄ generated by a drive circuit 89. Timing diagrams of these drive signals S85 ₁-S85 ₄ are also illustrated in FIG. 20. In FIG. 20, a high signal level of these timing diagrams represents an on-level of the corresponding drive signal S85 ₁-S85 ₄. An on-level of the drive signal is a signal level at which the corresponding switch is switched on. The drive signals S85 ₁-S85 ₄ may, for example, be generated dependent on the output voltage v80 of the buck converter 80, where, according to one embodiment, drive circuit 89 changes the switching state of the switches each time the output voltage v80 has decreased to 0. “Changing the switching state” means either switching the first and the fourth switches 85 ₁, 85 ₄ on and the other two switches off, or means switching the second and the third switch 85 ₂, 85 ₃ on and the other two switches off.

The buck converter 8 may have a conventional buck converter topology and may include a switch 83 connected in series with an inductive storage element 84, where the series circuit is connected between the first input terminal 21 of the converter unit 2 or the first output terminal 61 of a DC/DC converter (not shown), and the first output terminal 81 of the buck converter 80, respectively. A rectifier element 86 is connected between the second output terminal 82 (corresponding to the second input terminal 22) of the buck converter and a circuit node common to the switch 83 and the inductive storage element 84. The switch 83 can be implemented as a conventional electronic switch, such as a MOSFET or an IGBT, or as a GaN-HEMT. The rectifier element 86 can be implemented as a diode or as a synchronous rectifier. Further, a capacitive storage element 85, such as a capacitor, is connected between the input terminals of the buck converter 80, and an optional smoothing capacitor 89 is connected between the output terminals 81, 82.

The switch 83 of the buck converter 80 is driven by a PWM drive signal S83 generated by a control circuit or controller 87. The controller 87 of the buck converter 80 receives the reference signal S_(REF) from the controller 5 of the converter unit 2. The controller 87 of the buck converter 80 is configured to generate its output current i80 in correspondence with the reference signal S_(REF). This reference signal S_(REF) according to FIG. 19, unlike the reference signal S_(REF) of FIG. 11, does not have the waveform of the output current i1, but has the waveform of the rectified output current i1. This reference signal S_(REF) is also generated from the synchronization signal S_(v1) and the output current signal S_(i1).

The controller 5 for generating the reference signal S_(REF) according to FIG. 19 may correspond to the controllers illustrated in FIGS. 8 and 15 with the difference that the oscillating signal provided at the output of the oscillator 53 is rectified. An embodiment of the controller 5 according to FIG. 19 is illustrated in FIG. 21. This controller 5 corresponds to the controller according to FIG. 8 with the difference that the output signal of the filter 53 is received by a rectifier 58 that generates a rectified version of the oscillating output signal of the oscillator 53. Mathematically this is equivalent to forming the absolute value of the oscillating output signal of the oscillator 53. The reference signal S_(REF) is available at the output of the rectifier 58.

FIG. 22 illustrates a further embodiment of a controller 5 that can implemented in the DC/AC converter 4 of FIG. 19. The controller 5 of FIG. 22 is based on the controller 5 of FIG. 15 with the difference that the amplitude signal S_(AMPL) is generated from the input voltage signal S_(V3) voltage signal S_(V3) that represents the input voltage V3 provided by the DC source 3, and from the input voltage reference signal S_(REF-V3). The input voltage reference signal S_(REF-V3) can be generated by an MPPT, such as an MPPT 7 explained with reference to FIG. 11.

The control loops illustrated in FIGS. 15, 21 and 22 could, of course, be amended to be based on the control loop structure of FIG. 10 instead of FIG. 8.

Referring to FIG. 19, the controller 87 of the buck converters 80 can be implemented like a conventional controller for providing a PWM drive signal in a buck converter. The controller 86 receives the reference signal S_(REF) and an output current signal S_(i80), where the output current signal S_(i80) represents the output current vi80 of the buck converter 80. The controller 86 is configured to vary the duty cycle of the drive signal S83 such that the output current i80 of the buck converter 80 is in correspondence with the reference signal S_(REF). The functionality of this controller 86 corresponds to the functionality of the controller 67 illustrated in FIG. 13. In the embodiment illustrated in FIG. 19 the controller receives the output current signal S_(i1) representing the output current i1 and the synchronization signal S_(v1) for generating the reference signal S_(REF). However, this is only an example. It would also be possible to generate the reference signal S_(REF) based on signals representing the output voltage v80 and the output current i80 of the buck converter 80. In this case, the reference signal is generated such that output current i80 and the output voltage v80 of the buck converter 80 have a given phase difference.

The operating principle of a power converter circuit 1 including DC/AC converters as illustrated in FIG. 19 will now be explained with reference to FIGS. 1 and 19. The explanation will be based on the assumption that the voltage of the power grid 100 is a sinusoidal voltage so that an output current i1 with a sinusoidal waveform is desired. Further, it is assumed that the input powers of the individual DC/AC converters is zero, while the power grid voltage v_(N) is applied to the input terminals 11, 12 and the bridge circuits 85 in the individual converter units are in operation. In this case, the smoothing capacitors 89 of the buck converters are connected in series between the output terminals 11, 12. When the individual capacitors 89 have the same size, the voltage across each of these capacitors 89 is 1/n times the power grid voltage v_(N).

Assume now that the DC/AC converters receive an input power from the PV modules 3 connected thereto. The DC/AC converters then adjust their common output current i1 to be in phase with the external voltage v1 (the power grid voltage). The amplitude of the output current i1 is, in particular, controlled through the input voltage V3, where the current is increased when the voltage V3 increases, and the current is decreased when the voltage V3 decreases.

When the output current i1 provided by one DC/AC converter decreases, a current that corresponds to a difference between the output current i1 and the common current i1 _(OUT) is provided by the output capacitor C which causes the voltage v2 across the output capacitor C to decrease until the input power provided to the DC/AC converter corresponds to its output power. A decrease of the voltage v2 across the output capacitor 89 of one DC/AC converter 4 or one converter unit 2 causes an increase of the voltages across the output capacitors of the other converter units. This process proceeds until the converter unit 2 has settled in stable operation point at a lower output current i1. If the other converter units 2 at first continue to run at the same duty cycle, the increase of the voltages across their output capacitors leads to a reduction of their output currents i1 (and hence to a reduction of the common output current) in order to keep their output powers equal their input powers. When the output current i1 provided by one DC/AC converter increases so as to be higher than the common current i1 _(OUT), the corresponding output capacitor C is charged which results in an increase of the voltage across the output capacitor C of the one converter and a decrease of the voltage across the output capacitors of the other converters.

It became obvious from the explanation provided before that besides the control loops in the individual converter units 2 no additional control loop is required in order to control the output voltages of the individual converter units 2. The power converter circuit 1 with the converter units 2 is “self-organizing.” Referring to FIG. 1, assume that, for example, in the steady state the input power provided by the first DC source 3 ₁ to the first converter unit 2 ₁ would drop, for example because the corresponding PV array is shaded. The output voltage v2 ₁ of the corresponding converter unit 2 would then drop, while the output voltages of the other converter units 2 ₂, 2 _(n) would increase in order to meet the condition defined by equation (1). Further, the common output current i1 _(OUT) would decrease. The transient process is as follows. When the input power received by the first converter unit 2 ₁ decreases, the common output current i1 _(OUT) at first remains unchanged, while the output current i1 ₁ of the first converter unit 2 ₁ decreases. The decrease of the output current i1 ₁ and the unchanged common output current i_(OUT1) causes a discharging of the output capacitor C₁ of the first converter unit 2 ₁ so that the output voltage v2 ₁ decreases. A decrease of the output voltage of the first converter unit, however, causes an increase of the output voltages of the other converters, which now decrease their output currents in order to keep their output powers equal their input powers. The transition processes finishes when a “new” common output current i_(OUT) has settled in to which the individual output currents i1 correspond. This is a self-organizing and self-stabilizing process that does not require and additional control loop besides the control loops in the individual converter units 2 disclosed before.

FIG. 23 illustrates a further embodiment of a power converter circuit. In this power converter circuit two series circuits 1 _(I), 1 _(II) each including one group with a plurality of converter units 2 _(I1)-2 _(In) and 2 _(II1)-2 _(IIn) connected in series are connected in parallel between the output terminals 11, 12. Each of the series circuits 1 _(I), 1 _(II) can be implemented in accordance with the series circuit 1 of converter units 2 ₁-2 _(n) explained before. The converter units of the two groups (the two series circuits) are coupled to the same synchronization circuit 10 that can be implemented in accordance with one of the embodiments explained before. Of course, more than two series circuits each with a plurality of converter units can be connected in parallel.

Referring to the explanation herein before, the synchronization circuit 10 can be implemented as a voltage measurement circuit that measures the external AC voltage v₁ and that generates the at least one synchronization signal S_(v1) such that the synchronization signal is a continuous signal representing the external AC voltage v₁ and, therefore, having the same frequency and phase as the external AC voltage v₁. FIG. 24 illustrates a further embodiment of the synchronization circuit 10.

In the embodiment illustrated in FIG. 24, the synchronization circuit 10 receives the external AC voltage v₁ available at the output terminals 11, 12 and generates the synchronization signal S_(v1) as a continuous signal with a frequency and a phase that is dependent on the frequency and the phase of the external AC voltage v₁, respectively. According to one embodiment, the synchronization circuit 10 receives a phase-shift signal S_(PS) that defines a desired phase shift between the synchronization signal S_(v1) and the external AC voltage v₁. In the embodiment illustrated in FIG. 24, the synchronization circuit 10 includes a phase-shift circuit 110 that provides an output voltage v₁′. The output voltage v₁′ of the phase-shift circuit 110 has a phase shift relative to the external AC voltage v₁, with the phase shift being defined by the phase-shift signal S_(PS). A transmission circuit 120 receives the output voltage v₁′ of the phase-shift circuit 110 and generates the at least one synchronization signal S_(v1) transmitted to the individual converter units 2 (not illustrated in FIG. 24).

Referring to FIG. 25, the transmission circuit 120 may be implemented as a voltage divider having a plurality of voltage divider elements 120 ₁, 120 ₂, 120 _(n) connected in series. The voltage divider of the transmission circuit 120 is similar to the voltage divider illustrated in FIG. 3. The individual voltage divider elements 120 ₁-120 _(n) of the voltage divider 120 can be implemented like the voltage divider elements 10 _(i) explained with reference to FIGS. 4A to 4C and 5. Referring to FIG. 25, each of the voltage divider elements 120 ₁-120 _(n) provides a voltage v1 ₁′, v1 ₂′, v1 _(n)′, with each of these voltages representing one synchronization signal received by one converter unit 2 (not illustrated in FIG. 25) in the same way as the individual converter units 2 ₁-2 _(n) of FIG. 3 receive the individual voltages v1 ₁, v1 ₂, v1 _(n).

When employing a synchronization circuit 10 as illustrated in FIG. 24, a phase shift between the output currents i1 of the individual converter units 2 and the external AC voltage v1 can be adjusted through the phase-shift signal S_(PS), so that there is no need to individually provide phase shift signals (S_(φ) in FIGS. 15, 21 and 22) to the individual converter units 2. However, it is of course possible to additionally provide phase shift signals to the individual converter units 2.

Transmitting the at least one synchronization signal S_(v1) to the individual converter units through a voltage divider, as illustrated in FIG. 25, is only one possible embodiment. According to further embodiments, the at least one synchronization signal S_(v1) is transmitted to the individual converter units 2 via a signal bus, a radio path, or via a power line using power line communication. Of course, corresponding receiver circuits are employed in the converter units 2 in this case.

Referring to power line communication, standard power line communication circuits can be used for the communication between the synchronization circuit 10 and the individual converter units 2 since the output current because i_(OUT) of the converter circuit is an AC current. In this case, the power line of the converter circuit 1, which is the line carrying the output current i_(OUT) and connecting the outputs of the individual converter units 2 is used for the communication. A first power line communication interface (not shown) coupled to the power line receives the synchronization signal S_(V1) and forwards the synchronization signal S_(v1) suitably modulated via the power line to the individual converter units 2. Each converter unit includes a corresponding power line communication interface coupled to the power line and configured to receive and demodulate the modulated synchronization signal S_(v1).

According to a further embodiment, that is illustrated in dashed lines in FIG. 24, the synchronization circuit does not only receive a phase-shift signal S_(PS) but additionally to the phase shift signal S_(PS) or instead of the phase shift signal S_(PS) receives a control signal S_(CTRL) through which other parameters of the synchronization signal S_(V1), such as the frequency and/or the amplitude of the synchronization signal S_(V1) can be adjusted. In this embodiment, the synchronization signal S_(V1) can be generated independent of the external AC voltage v₁, which may be helpful in some operation scenarios explained below.

Referring to the explanation herein before, the synchronization signal S_(v1) received by each converter unit 2 can be a continuous signal that is continuously transmitted from the synchronization circuit 10 to the converter units 2. Each of the converter units 2 continuously generates its corresponding output current i1 in accordance with the synchronization signal S_(v1), which means with a frequency and a phase defined by the synchronization signal S_(v1).

According to a further embodiment, the synchronization signal S_(v1) is a pulse signal including a sequence of signal pulses and the individual converter 2 units are configured to generate a continuous signal having a frequency and a phase from the pulse signal.

FIG. 26 illustrates an embodiment of a converter unit 2 that is configured to receive a pulse signal as a synchronization signal S_(v1). The converter unit 2 of FIG. 26 corresponds to the converter units of FIGS. 5 and 11 and additionally includes a signal generator 20 that receives the pulsed synchronization signal S_(v1) and that is configured to generate a continuous sinusoidal synchronization signal S_(v1)′ from the pulsed signal S_(v1). In this embodiment, the continuous synchronization signal S_(v1)′ provided at the output of the signal generator 20 is received by the control circuit 5 and is processed in the control circuit 5 in the same way as a continuous sinusoidal synchronization signal S_(v1) explained herein before. The DC/AC converter 4 and the optional DC/DC converter 6 can be implemented as explained before and below.

According to one embodiment, the pulsed synchronization signal S_(v1) is a periodic signal having signal pulses that are equally distant, and signal generator 20 is configured to generate a sinusoidal signal S_(v1)′ from the pulsed signal S_(v1). According to one embodiment, the signal generator 20 generates the sinusoidal synchronization signal S_(v1)′ such that a zero crossing of the sinusoidal signal S_(v1)′ occurs each time a signal pulse of the pulsed synchronization signal S_(v1) occurs. In this embodiment, the mutual distance of the signal pulses defines the frequency of the continuous synchronization signal S_(v1)′ generated by the signal generator 20 and the absolute position of the individual signal pulses on the time scale defines the phase of the continuous synchronization signal. An embodiment of a signal generating 20 configured to receive a pulsed synchronization signal S_(v1) and configured to generate a continuous sinusoidal synchronization signal S_(v1)′ with a frequency and a phase as defined by the pulsed synchronization signal S_(v1) is illustrated in FIG. 27. Timing diagrams of signals occurring in this signal generator are illustrated in FIG. 28.

Referring to FIG. 27, the signal generator includes an integrator 202 receiving the pulsed synchronization signal S_(v1) as a clock signal. A timing diagram of an embodiment of the pulsed synchronization signal S_(v1) is illustrated in FIG. 28. The integrator is configured to integrate a constant signal C received at a second input beginning with each signal pulse of the pulsed synchronization signal S_(v1)′. An output signal of the integrator 202 is a ramp signal S_(RAMP) with a frequency corresponding to the frequency of the pulsed synchronization signal S_(v1)′. The constant signal is provided by a calculation unit 201 that receives pulsed signal S_(v1) and calculates the constant signal C to be proportional to the frequency of the pulsed synchronization signal S_(v1)′ or to be inversely proportional to a time period T (see FIG. 28) of the pulsed signal S_(v1)′. In the steady state, the slope of the individual ramps of the ramp signal S_(RAMP) is dependent on the frequency (and decreases when the frequency is reduced) and the amplitudes of the individual ramps are equal. According to one embodiment, the calculation unit 201 calculates the constant value C in each cycle of the pulsed signal S_(v1)′ and provides the calculated value to the integrator in the next cycle. Thus, a frequency change of the synchronization becomes effective in the generation of the ramp signal S_(RAMP) with a delay of one cycle of the pulsed signal.

Referring to FIG. 27, a trigonometric function generator 203 receives the ramp signal S_(RAMP) and generates the continuous synchronization signal S_(v1)′ by calculating the sine or the cosine of instantaneous values of the ramp signal S_(RAMP). The resulting continuous synchronization signal S_(v1)′ is illustrated in FIG. 28. In the embodiment illustrated in FIGS. 27 and 28 the continuous synchronization signal S_(v1)′ has a zero crossing from negative to positive signal values each time a signal pulse of the pulsed synchronization signal occurs.

Of course, the signal generator of FIG. 27 could easily be modified to generate the continuous synchronization signal S_(v1)′ such that with each pulse of the pulsed signal S_(v1) a zero crossing from positive to negative signal values occurs.

According to one embodiment, the pulsed synchronization signal S_(v1) is only transmitted for a short time when a frequency and/or phase of the pulsed signal changes. This means, only a short sequence with some cycles of the pulsed signal S_(v1) is transmitted, while after the transmission of the sequence the pulsed signal is interrupted for a time period significantly longer than one cycle period. This interruption may be several seconds or several minutes. In this embodiment, a clock generator receives the pulsed signal S_(v1). The clock generator is configured to measure the frequency of the pulsed signal S_(v1) and to generate a clock signal provided to the integrator with a frequency corresponding to the measured frequency of the pulsed signal S_(v1). The clock generator is, in particular configured to store the frequency information and to generate the clock signal even in those time periods when the pulsed signal S_(v1) has been switched off and updates the frequency each time a new sequence of the pulsed signal S_(v1) is transmitted. Equivalently, the calculation unit stores the calculated value C until a new sequence of the pulsed signal S_(v1) is transmitted that allows the calculation unit 201 to re-calculate the constant value.

According to a further embodiment, the synchronization signal S_(v1) is an AC signal that is only transmitted for a certain time period, such as, for example, for a duration corresponding to only several periods of the AC signal. In this embodiment, the signal generator 20 is configured to evaluate a frequency and a phase information of the synchronization signal S_(v1) and is configured to generate the continuous synchronization signal S_(v1) based on this frequency and time information. In this embodiment, the synchronization signal S_(v1) may be transmitted only once at the beginning of the operation of the power converter circuit 1 to the individual converter units, or may be transmitted periodically during the operation of the power converter circuit 1.

According to one embodiment, the AC synchronization signal S_(v1) received by each converter unit 2 is the voltage v2 across the output capacitor C of each converter unit 2 before the power converter circuit 1 is activated, that is before the individual converter units 2 are activated and generate output currents i1. Referring to FIG. 1, when an external voltage v₁ is applied to the output 11, 12 and when the individual converter units 2 are deactivated (not yet activated), the voltages v2 across the output capacitors C are in phase with the external voltage v₁ and each of these voltages v2 is a share of the external voltage v₁. Thus, each of the converter units 2 can then use the voltage across its output capacitor C as an AC synchronization signal that is only received for a certain time period, namely a time period before the converter units 2 are activated. The signal generator 20 (see FIG. 26) in each of the individual converter units evaluates a frequency and a phase information of the corresponding synchronization signal S_(v1) (the voltage v2) and generates the continuous synchronization signal S_(v1)′ based on this frequency and time information. After the converter units 2 have been activated, there may be operation scenarios in which at least some of the individual output voltages v2 are not in phase with the external voltage v₁, so that after the converter units 2 have been activated a continuous synchronization signal in each converter unit 2 is used to generate the output current i1. In this embodiment, the synchronization circuit 10 measures the output voltages v2 of the individual converter units 2. This will be explained with reference to FIG. 35 in further detail below.

An embodiment of a signal generator 20 that is configured to generate a continuous (sinusoidal) synchronization signal S_(v1)′ from a synchronization signal S_(v1) that is available for only several periods is illustrated in FIG. 29. The signal generator of FIG. 29 is based on the signal generator of FIG. 27 and additionally includes a zero crossing detector 205 receiving the synchronization signal S_(v1) and configured to generate a pulse signal. The pulse signal generated by the zero crossing detector includes a signal pulse each time a positive or a negative zero crossing is detected. The pulse signal provided by the zero crossing detector 205 is then processed by the clock generator 204, the calculation unit 201, the integrator 202, and the trigonometric function generator 203 as explained with reference to FIGS. 27 and 28. In this embodiment, the continuous synchronization signal S_(v1)′ is synchronized to the synchronization signal S_(v1) during that time period when the synchronization signal S_(v1) is available and, after the synchronization signal has been switched off, continues to generate the continuous synchronization signal S_(v1)′ based on the frequency and phase information stored in the clock generator 204 and the calculation unit 201.

According to a further embodiment, the synchronization signal S_(v1) transmitted to the individual converter units corresponds to the frequency and phase signal S_(ωt) explained with reference to FIGS. 15, 21 and 22. In this embodiment, the signal generator 20 can be omitted and the control circuit 5 can be simplified by omitting the PLL 51.

In each of the individual cases where different signal waveforms of the synchronization signal S_(v1) have been discussed, the synchronization signal S_(v1) can be generated by the synchronization circuit 10 connected between output terminals 11, 12.

So far, the operation of the power converter circuit in a normal operation mode has been explained. In the normal operation mode, each of the individual converter units 2 is configured to generate its output current i1 such that the output current i1 has a frequency and the phase as defined by the synchronization signal S_(v1) received by the converter unit 2. Besides the normal operation mode other operation modes of the power converter circuit 1 as well.

According to one embodiment, that is schematically illustrated in FIG. 30, the power converter circuit 1 is either operated in the normal mode 901 or in a standby mode 902. In the standby mode 902 the individual converter units 2 are deactivated so that the output currents i1 of the individual converter units 2 are zero, but may again be activated.

For example, the power converter is, e.g., in the standby mode, when the supply voltages (V3 ₁-V3 _(n) in FIG. 1) provided by the DC power sources are too low for generating the output currents i1. When the individual DC power sources 3 ₁-3 _(n), are implemented as PV modules, this may occur at night.

The power converter circuit 1 switches from the normal mode 901 to the standby mode 902 when a shut-down condition is met, and changes from the standby mode 902 to the normal mode when a start-up condition is met. The process of switching the power converter circuit 1 from the normal mode to the standby mode will be referred to as shut down and a sequence of operations involved in this process will be referred to as shut-down sequence in the following. The process of switching the power converter circuit 1 from the standby mode to the normal mode will be referred to as start-up and a sequence of operations involved in this process will be referred to as start-up sequence in the following.

The power converter circuit 1 may include an operation mode controller that defines the operation mode of the power converter circuit 1. With other words, the operation mode controller 50 controls the overall operation of the power converter circuit 1. FIG. 31 illustrates a block diagram of a power converter circuit 1 that includes an operation mode controller 50. The operation mode controller 50 can be implemented as a microprocessor, an ASIC, a digital signal processor, a state machine, or the like.

In the embodiment illustrated in FIG. 31, the operation mode controller 50 receives at least one operation parameter of the power converter circuit 1 from a measurement unit 600, is configured to control a connection circuit 70 connected between the series circuit with the individual converter units 2 ₁-2 _(n), and the output terminals 11, 12, and is configured to control the synchronization unit 10. The measurement circuit 600 is configured to measure at least one of the output current i_(OUT) of the series circuit with the converter units 2 ₁-2 _(n), and a voltage v_(OUT) across the series circuit 2 ₁-2 _(n). As schematically illustrated in FIG. 31, the measurement circuit 600 may include a current measurement circuit 600 for measuring the output current i_(OUT), and a voltage measurement circuit 602 for measuring the output voltage v_(OUT). The output voltage v_(OUT) across the series circuit corresponds to the external AC voltage v₁ when the series circuit is connected to the output terminals 11, 12. The connection circuit 70 that is configured to either connect the series circuit 2 ₁-2 _(n) to the output terminals 11, 12 or to disconnect the series circuit 2 ₁-2 _(n) from the output terminals 11, 12 may include two switches, namely a first switch 701 connected between the series circuit 2 ₁-2 _(n) and the first output terminal 11 and a second switch 702 connected between the series circuit 2 ₁-2 _(n) and the second output terminal 12. These switches 701, 702 can be implemented as conventional switches, such as relays or semiconductor switches (MOSFETs, IGBTs, etc.). Referring to FIG. 31, the connection circuit 70 may include an optional third switch 703 connected in parallel with the series circuit 2 ₁-2 _(n). This switch 703 may be closed when an output voltage of the series circuit with the individual converter units 2 is above a given voltage threshold, in order to limit the output voltage. Optionally, a resistor or another type of current limiting element is connected in series with this switch 703.

In FIG. 31, signal S600 provided by the measurement circuit 600 to the operation mode controller 50 represents the at least one operation parameter measured by the measurement circuit 600. This measurement signal S600 includes information on at least one of the output current i_(OUT) and the output voltage v_(OUT). Signal S70 in FIG. 31 schematically illustrates a control signal generated by the operation mode controller 50 and received by the connection circuit 70. Dependent on the control signal S70, the connection circuit 70 connects the series circuit to the output terminals 11, 12, disconnect the series circuit from the output terminals 11, 12, or short-circuits the series circuit 2 ₁-2 _(n).

Referring to FIG. 31, the operation mode controller 50 further controls the synchronization circuit 10 that generates the synchronization signal S_(v1). In FIG. 31, only the control signal S_(CTRL) is drawn to be received by the synchronization circuit 10. The control signal S_(CTRL) defines the signal parameters of the synchronization signal S_(v1), such as frequency, phase and amplitude. As controlled by the control signal S_(CTRL) the synchronization signal S_(v1) can be dependent on the external AC voltage v₁ that is also received by the synchronization circuit 10, such as have a given phase shift (zero or other than zero) relative to the external AC voltage, or the synchronization signal S_(v1) can be independent of the external AC voltage v₁. Referring to the explanation below, there may be operating scenarios (such as fault ride through) where it is necessary to generate the synchronization signal S_(v1) independent of the external AC voltage v₁.

In the power converter circuit of FIG. 31, the synchronization signal S_(v1) is not only used in the normal mode to provide a synchronization information to the individual converter units 2 for generating the output currents i1, but is also used in the standby mode for signaling the individual converter units 2 that a change from the standby mode to the normal mode is desired. In this power converter circuit 1, the operation mode controller 50 has the synchronization circuit 10 generate the synchronization signal S_(v1) with a standby waveform in the standby mode. The standby waveform is a waveform that is different from the signal waveform of the synchronization signal S_(v1) in the normal mode. According to one embodiment, the standby waveform is a waveform with a constant signal value, such as zero.

FIG. 32 illustrates an embodiment of a converter unit 2 that is configured to evaluate the operation mode information included in the synchronization signal S_(v1) and that can be operated in a normal mode or a standby mode. The overall power converter circuit 1 is in the normal mode when each of the converter units 2 is in the normal mode and is in the standby mode when each of the converter units is in the standby mode 2. The converter unit 2 shown in FIG. 32 is based on the converter units of FIGS. 5, 11 and 26, where the DC/DC converter 6 and its control circuit 7, and the signal generator 20 are optional. The converter unit 2 includes an operation mode unit 30 that receives the synchronization signal S_(v1) and that is configured to evaluate the synchronization signal S_(v1). The operation mode unit 30 is, in particular, configured to detect a change of the synchronization signal S_(v1) from the standby waveform to the normal waveform, the latter being the usual waveform in the normal mode. Referring to the explanation above, the normal waveform can be a continuous AC waveform, a pulsed signal waveform, or an AC waveform with only some periods.

The operation mode unit 30 is further configured to control the DC/AC converter 4, in particular to activate the DC/AC converter 4 in the normal mode and to deactivate the DC/AC converter in the standby mode. When the converter unit 2 further includes the DC/DC converter 6, the operation mode unit 30 further controls the operation (activates or deactivates) of the DC/DC converter 6. When the DC/AC converter 4 and the optional DC/DC converter 6 is activated, the operating principle of the converter unit 2 corresponds to the operating principle explained before, which means the converter unit 2 provides an output current i1 in accordance with the synchronizations signal S_(v1). When the DC/AC converter 4 and the optional DC/DC converter 6 are deactivated, the switches (see FIGS. 6 and 19) in the DC/AC converter 4 and the DC/DC converter are either switched off, or some of the switches are permanently switched on. This is explained in greater detail below.

In the standby mode, the operation mode controller 50 either disconnects the series circuit 2 ₁-2 _(n) from the output terminals 11, 12 and, therefore, from the external AC voltage v₁, or leaves the series circuit 2 ₁-2 _(n) connected to the output terminals 11, 12.

Embodiments of start-up sequences for switching from the standby mode to the normal mode are explained below. For explanation purposes it is assumed that the individual DC power sources are PV modules. In this case, a start-up sequences is required at least once a day, namely in the morning after sunrise.

Start-Up Sequence A

A first embodiment of a start-up sequence (start-up sequence A) is illustrated in FIG. 33. In this embodiment, the individual converter units 2 in the standby mode 902 are configured to pass the input voltage V3 from the input terminals 21, 22 through to the output terminals 23, 24, and the operation mode controller 50 is configured to have the connection circuit 70 disconnect the series circuit 2 ₁-2 _(n) from the output terminals 11, 12.

The input voltage V3 can be connected through the converter unit 2 to the output terminals 23, 24 by switching on switches in the DC/AC converter 4 and the optional DC/DC converter 6 in a specific configuration. When, for example, the DC/AC converter 4 is implemented with a H4-bridge as illustrated in FIG. 6, the input voltage V3 can be connected through to the output terminals 23, 24 by permanently switching on the first switch 42 ₁ and the fourth switch 42 ₄. When the optional DC/DC converter 6 is a boost converter, as illustrated in FIG. 12, the switch 65 is permanently switched off, and when the optional DC/DC converter 6 is a buck converter, as illustrated in FIG. 14, the switch 65 is permanently switched on. The switching states of the switches in the DC/AC converter 4 and the DC/DC converter 6 in the standby mode is governed by the operation mode unit 30.

When, for example, the DC/AC converter is implemented with a buck converter and an unfolding bridge as illustrated in FIG. 19, the input voltage V3 can be connected through to the output terminals 23, 24 by permanently switching on the first switch 85 ₁ and the fourth switch 85 ₄ in the unfolding bridge 85 and by switching on the switch 83 in the buck converter 80.

After sunrise, the input voltage V3 at the input terminals 21, 22 and, therefore, the output voltage v2, which at this stage is a DC voltage, increases. The operation mode controller 50 is configured to detect the output voltage v_(OUT). The output voltage v_(OUT) is the sum of the output voltages v2 of the individual converter units 2, where this output voltage v_(OUT) increases after sunrise when the solar power received by the PV modules increases. When the output voltage v_(OUT) reaches a given threshold voltage v_(OUT-TH), the operation mode controller 50 controls the synchronization circuit 10 to generate the synchronization signal S_(v1) with the normal waveform has the connection circuit 70 connect the series circuit 2 ₁-2 _(n) to the output terminals 11, 12. Referring to the explanation before, the synchronization signal S_(v1) in a normal mode can be a continuous AC signal, a periodic pulse signal, or an AC signal for a limited time duration.

The operation mode unit 30 detects the change of the synchronization signal S_(v1) from the standby level to the normal level. The operation mode unit 30 then activates the DC/AC converter 4 and the optional DC/DC converter 6 to operate as explained with reference to FIGS. 1 to 23 before. According to one embodiment, the DC/AC converter 4 and the optional DC/DC converter 6 are activated at the time of a zero crossing of the synchronization signal S_(v1), so as to ramp up the output current i1.

According to one embodiment, not only frequency and phase of the output current i1, but also the amplitude of the output current i1 is controlled during the start-up phase so as to, e.g., continuously increase the output current in the start-up phase. The output current i1 of each converter 2 can be controlled by controlling the input power of the converter 2. Controlling the input power is possible in each converter topology in which the input voltage V3 is controlled, that is in each topology where the input voltage V3 is adjusted dependent on an input voltage reference signal S_(V3-REF). In the normal mode, the input voltage reference signal S_(v3-REF) may be generated by an MPP tracker (see, circuit block 7 in FIGS. 11 and 32) that serves to operate PV modules 3 providing the input voltage V3 in an optimum operation point. In order to control the input voltage V3 and, therefore, in order to control the output current i1 during start-up, the operation mode control circuit 30 can be configured to provide the input voltage reference signal S_(REF-V3) during start-up or can be configured to control the MPP tracker 7 during start-up. This is schematically illustrated in dotted lines in FIG. 32. During the start-up phase, the PV modules 3 are not necessarily operated in their MPP. According to one embodiment, the operation mode control circuit 30 increases the input voltage reference signal S_(REF-V3) stepwise in two, three or more steps, so as to stepwise increase the amplitude of the AC output current i1 of the individual converter units 2.

When in the converter unit 2 of FIG. 32, the DC/AC converter 4 includes a buck converter 80 and an H4-bridge 85, as illustrated in FIG. 19, the buck converter 80 can be configured to control the input voltage V3. The DC/DC converter 6 may be omitted in this case. An embodiment of a control circuit 5 that is configured to control the input voltage V3 in the DC/AC converter 4 of FIG. 19 is illustrated in FIG. 22. While in the normal mode, the input voltage reference signal S_(V3-REF) is provided by an MPP tracker (not illustrated in FIGS. 19 and 22), the input voltage reference signal S_(V3-REF) may be provided by the operation mode unit 30 during the start-up phase in order to control the output current i1 during the start-up phase.

Switching on the switches in the DC/AC converter 4 and the optional DC/DC converter 6 in the standby mode requires a power supply. Referring to FIG. 32, each converter unit 2 includes a power supply unit 40 that provides for the power supply of the individual components in the converter unit 2. The power supply unit 40 is either connected to the input terminals 21, 22, to the output terminals 23, 24 or, when there is a DC link capacitor between the DC/DC converter 6 and the DC/AC converter 4, to the DC link capacitor.

When the power supply unit 40 is connected to the input terminals 21, 22, energy for switching on the switches in the DC/AC converter 4 and the DC/DC converter 6 is, of course, only provided when an input voltage V3 other than zero is provided by the DC power source. Thus, after sunrise, the input voltage V3 first powers the power supply unit 40, which powers the components in the power converter unit 2, which then passes the input voltage V3 through to the output terminals 23, 24, the output voltage v2 is then detected by the operation mode controller 50, which then has the converter unit 2 change to the normal mode by having the synchronization circuit 10 change the synchronization signal S_(v1) from the standby waveform to the normal waveform. Before solar power is provided to the PV modules, i.e., when the input voltage V3 is zero, each of the switches in the converter unit 2 is switched off and the converter unit cannot be activated. This operation mode can be referred to as shut-off mode.

Start-Up Sequence B

A second embodiment of a start-up sequence (start-up sequence B) is illustrated in FIG. 34. In this embodiment, the operation mode controller 50 leaves the series circuit 2 ₁-2 _(n), connected to the output terminals 11, 12 when the power converter circuit 1 is in the standby mode. The individual converter units 2 are deactivated, so that the output current i_(OUT) is zero and the output voltage v_(OUT) corresponds to the external AC voltage v₁. The external AC voltage v₁ charges the input capacitor of the DC/AC converter 4, which is the DC link capacitor when a DC/DC converter 6 and a DC/AC converter 4 are employed. The charging of the input capacitor of the DC/AC converter 4 is explained for the DC/AC converter topologies of FIGS. 6 and 19 below. Referring to FIG. 6, the switches of the H4-bridge each have a freewheeling element 42 ₁-42 ₄. Via these freewheeling elements the input capacitor 41 (or the DC link capacitor 600 of FIG. 11) is charged to the peak value of the AC voltage v2 between the output terminals 23, 24, when the switches 42 ₁-42 ₄ are switched off. Thus, in the standby mode, the operation mode unit (30 in FIG. 32) controls the switches of a DC/AC converter 4 implemented with a H4 -bridge to be switched off.

When the DC/AC converter 4 is implemented with an unfolding bridge 85 as illustrated in FIG. 19, the DC link capacitor 89 is charged through freewheeling elements (not illustrated in FIG. 19) of the individual switched 85 ₁-85 ₄ to the peak value of the AC input voltage v2.

In this embodiment, the power supply unit 40 is connected to the input capacitor of the DC/AC converter 4 or to the DC link capacitor which permanently provides for a power supply of the converter unit 2.

While in the start-up sequence A the power converter automatically enters the normal mode when sufficiently high input voltages V3 are provided, an additional trigger signal is required in the start-up sequence B informing the operation mode controller 50 that the power converter circuit 1 may switch from the standby mode to the normal operation mode. According to one embodiment, the trigger signal is a signal indicating the sunrise and, therefore the time when enough solar power is expected to be received by the individual PV modules in order to successfully switch from the standby mode to the normal mode. This trigger signal can be provided from an external source to the operation mode controller 50 or can be calculated in the operation mode controller 50 dependent on the specific date, the geographical position of the PV modules and a table that includes the time of sunrise at the geographical position at different dates. This signal triggering a switching from the standby mode to the normal mode will be referred to as trigger signal or sunrise signal in the following.

Start-Up Sequence C

According to a further embodiment (start-up sequence C), which includes features from both, the start-up sequences A and B, the operation mode controller 50 leaves the series circuit 2 ₁-2 _(n) disconnected from the output terminals 11, 12 in the standby mode. Further, the converter units 2 are configured to pass through the input voltage V3 to the output terminals 23, 24 in the standby mode. In this embodiment, switching of the power converter circuit 1 from the standby mode to the normal mode is initiated by the sunrise signal. Again, switching from the standby mode to the normal mode includes changing the waveform of the synchronization signal S_(v1) from the standby waveform to the normal waveform.

There may be several reasons for the power converter circuit 1 to switch from the normal mode to the standby mode. According to one embodiment, the operation mode controller 50 is also configured to cause the power converter circuit 1 to switch from the normal mode to the standby mode when the operation mode controller 50 detects the occurrence of a shut-down condition. Shut-down information can be transmitted from the operation mode controller 50 to the individual converter units 2 in different ways. When a shut-down information is received by the individual converter units 2, the converter units are deactivated and enter the standby mode.

As explained above in connection with start-up sequence I, the operation mode controller 50 can be configured to only start-up the power converter circuit 1 when the output voltage v_(OUT) in the standby mode is higher than a given reference voltage. When the output voltage v_(OUT) is too low, this may have several reasons. First, the solar power received by the PV modules can be too low. Second, there are not enough converter units 2 connected in series.

Transmission of Shut-Down Information I

According to a first embodiment, the synchronization signal S_(v1) is used to transmit shut-down information from the operation mode controller 50 to the individual converter units 2. Independent of the waveform of the synchronization signal S_(v1) in the normal mode, the operation mode controller 50 simply controls the synchronization circuit 10 to generate a standby waveform of the synchronization signal S_(v1). The operation mode units 30 in the individual converter 2 are configured to detect the standby waveform and to deactivate the corresponding converter unit upon detection of the standby waveform. In the standby mode, the output currents i1 of the individual converter units 2 become zero.

Transmission of Shut-Down Information II

According to a further embodiment, the operation mode controller 50 has the connection circuit 70 to disconnect the series circuit from the output terminals 11, 12 when a switching from the normal mode to the shut-off mode is desired. When the series circuit 2 ₁-2 _(n) is disconnected from the power grid and when the converter units 2 are still in the normal mode, the output current provided by each converter unit 2 causes the output voltages v2 of the individual converter units 2 to increase, so that the overall output voltage v_(OUT) increases. In this embodiment, the converter units 2, are configured to detect their output voltage v2 and are configured to enter the standby mode when the output voltage increases to an overvoltage threshold. According to one embodiment, the operation mode unit 30 of each converter unit 2 monitors the output voltage v2 and compares the output voltage with the overvoltage threshold and shuts down the converter unit 2 when the output voltage v2 reaches the overvoltage threshold. According to one embodiment, the overvoltage threshold is chosen to be dependent on the voltage blocking capability of the semiconductor switches employed in the DC/AC converter 4 of each converter unit 2.

In this embodiment, there is no direct transmission of information from the operation mode controller 50 to the individual converter units 2. Instead, the switching information is provided by allowing the output voltages v2 of the individual converter units 2 to increase to the overvoltage threshold.

Also in those cases in which the synchronization signal is used to transmit the switching information, so that there is no intended overvoltage in the individual converter units 2, an overvoltage of the output voltages of one converter unit 2 may occur, e.g., when disconnecting the series circuit 2 ₁-2 _(n) from the power grid. Thus, an overvoltage protection may be implemented in the individual converter units 2 in each case.

Some embodiments of shut-down conditions (errors) that can be detected by the operation mode controller are explained below. Dependent on the type of error, the operation mode controller 50 may try to restart the power converter circuit 1 after a certain time, or may keep the power converter circuit shut down.

Low Output Current

According to one embodiment, the power converter circuit switches from the normal mode to the standby mode, when the output current falls below a given current threshold. This transfer is initiated by the operation mode controller 50 that compares the output current i_(OUT) based on information received from the measurement unit 600 with the current threshold. The current threshold is, for example, chosen from a range of between 0.2 A and 0.5 A.

Undervoltage Condition

Another type of error may occur when the solar power received by each of the converter units 2 is low. In this case, the output current i_(OUT) of the series circuit with the individual converter units 2 may have a non-sinusoidal waveform such that the waveform of the output current i_(OUT) follows the waveform of the external AC voltage v₁ when the instantaneous value of the output voltage v₁ is low, and that the output current i_(OUT) is kept on a constant value or even decreases at higher instantaneous values of the output current. This type of error can be detected by the operation mode controller 50 by comparing the waveform of the output voltage v_(OUT) or the external AC voltage v₁, respectively, and the output current i_(OUT). When this type of error is detected by the operation mode controller 50, the operation mode controller 50 initiates one of the shut-down sequences explained above in order to switch the power converter circuit 1 into the standby mode.

Phase Difference

According to a further embodiment, the operation mode controller 50 is configured to measure a phase difference between a phase of the external AC voltage v₁ and the output current i_(OUT). When this phase difference is larger than a desired phase difference, namely the phase difference given by the synchronization signal S_(v1) v₁ and/or the phase difference as defined by the phase signals S_(φ), two different courses of action initiated by the operation mode controller 50 are possible. When, for example, the phase difference between the output voltage i_(OUT) and the external AC voltage v₁ is below a first phase difference threshold, the phase difference of the synchronization signal S_(v1) relative to the external AC voltage v₁ can be changed in order to readjust the phase difference between the output current i_(OUT) and the external AC voltage v₁. When, however, the phase difference is above the phase-difference threshold, the operation mode controller 50 may shut down the power converter circuit 1 using one of the shut-down sequences explained before.

Evaluation of the phase difference may particularly be relevant in those cases in which the synchronization signal S_(v1) is only available at or before start of the normal operation of the power converter circuit or only at certain times during the normal operation of the power converter circuit and in which a continuous synchronization signal S_(v1)′ is generated from the synchronization signal S_(v1).

Sunset

Similar to having the power converter start-up using a trigger signal at sunrise, a corresponding trigger signal can be used to shut-down the power converter circuit at sunset.

Automatic Shut Down

When, for example, the solar power received by some of the PV modules is much lower than the solar power received by other modules, the output voltage of the converter units 2 connected to the PV modules receiving a low solar power decreases, while the output voltage of the other converter units 2 increases. This mechanism has been explained in detail herein before. When there are several PV modules that receive a significantly lower solar power than other modules, the external AC voltage v₁ applied to the output terminals 11, 12 may result in an overvoltage at the outputs of the other converter units 2. The converter units 2 having an overvoltage may shut down, which results in an overvoltage at the outputs of other converter units 2, which are then shut down. This proceeds, until each of the converter units 2 is shut down. When the converter units 2 are shut down, the output current becomes zero. In this case, the individual converter units 2 automatically shut down, so that no shut-down information has to be transmitted from the operation mode controller 50 to the individual converter units 2. A decrease of the output current to zero is detected by the operation mode controller 50 which may then cause the synchronization circuit 10 to generate a standby waveform of the synchronization signal S_(v1).

The operation mode controller 50 may not only be configured to monitor the operation of the power converter circuit 1, but may also be configured to monitor the power grid, specifically the external AC voltage v₁, in order to shut down the power converter circuit 1 when an error is detected.

Anti-Islanding

A first type of grid error that may occur is “islanding.” In this case, the power grid has a high input impedance at the input terminals 7, 12. This error can be detected by having the series circuit with the converter units 2 generate a constant output current i_(OUT) or an AC output current i_(OUT) with a frequency that is different from the frequency of the external AC voltage v₁. As explained hereinbefore, the frequency of the output current i_(OUT) (which is zero, when the output current i_(OUT) is constant) can be adjusted through the synchronization signal S_(v1).

In order to test for the occurrence of an islanding error, the operation mode controller 50 can be configured to have the synchronization circuit 10 generate the synchronization signal with a frequency other than the frequency of the external AC voltage v₁. In a test mode in which the operation mode controller 50 changes the output current i_(OUT) as explained before, the operation mode controller 50 compares the waveform of the output current i_(OUT) with the waveform of the external voltage v₁ available at the output terminals 11, 12. When the waveform of the external voltage v₁ follows the waveform of the output current i_(OUT), the power grid has a high input impedance (or has even been switched off distant to the output terminals 11, 12). In this case, the operation mode controller shuts down the power converter circuit 1.

Interruption of Grid Voltage

According to one embodiment, the operation mode controller 50 is configured to monitor the external AC voltage v₁ and is configured to shut down the power converter circuit 1 when the external AC voltage v₁ is switched off or interrupted.

Fault Ride Through

According to one embodiment, the operation mode controller 50 does not shut down the power converter circuit 1 immediately when the external AC voltage v₁ is interrupted, but has the series circuit generate an AC output current i_(OUT) for a specified time period, such as, for example, several milliseconds (ms). The operation mode controller 1 shuts down the power converter circuit 1 when the external AC voltage v₁ has not recovered after this specified time period. The operation mode in which an AC output current i_(OUT) is provided although the external AC voltage v₁ has been interrupted, is out phase, lower than usual, distorted, short-circuited, etc., is referred to as “fault ride through.”

In the fault-ride-through mode, the synchronization information in accordance to which the individual converter units 2 generate their output currents i1 can be provided in different ways. An embodiment, in which the synchronization information is only transmitted at the beginning of the normal mode and in which a continuous synchronization signal is generated (in the signal generator 20) in the individual converter units 2, no additional synchronization information needs to be provided in the fault-ride-through mode. When, however, the individual converter units 2 require a continuous synchronization signal, and when the synchronization signal in the normal mode is generated from the external AC voltage v₁, the synchronization circuit 10 in the fault-ride-through mode continuous to generate a continuous synchronization signal based on the frequency and phase information of the synchronization signal generated before in the normal mode, i.e., before an interruption of the external AC voltage v₁ has been detected.

Reactive Power Generation

The power converter circuit 1 may even be used to stabilize the voltage on the power grid.

Referring to the explanation provided before, in the normal mode, the output current iOUT generated by the series circuit of the individual converter units 2 has a frequency and a phase as defined by the synchronization signal Sv1. The frequency and the phase of the synchronization signal Sv1 can be adjusted by the operation mode controller 50. In the normal mode, the synchronization signal Sv1 is usually generated such that the frequency information included in the synchronization signal Sv1 corresponds to the frequency of the external AC voltage v1 and the phase information corresponds to the phase of the external AC voltage v1. In this case, the output current iOUT is in phase with the external AC voltage v1.

However, there may be situations in which it is desired to have a phase difference between the output current iOUT and the external AC voltage v1, in order to provide reactive power to the power grid so as to stabilize the voltage on the power grid. This phase difference can easily be adjusted by suitably adjusting the phase information included in the synchronization signal Sv1. According to one embodiment, the operation mode controller 50 receives an external signal from a utility provider, where this external signal includes a desired phase difference between the output current iOUT and the external voltage v1. The external signal can be provided to the operation mode controller via conventional communication channels, such as radio channels, power lines, or the internet.

According to a further embodiment, the operation mode controller 50 measures the output power provided by the power converter circuit 1 to the power grid and adjusts the phase difference between the output current iOUT and the external AC voltage v1 dependent on the output power. According to one embodiment, the phase difference increases, so as to increase the reactive power provided to the net, when the output power provided by the power converter circuit 1 increases.

Active Power Derating

According to a further embodiment, the operation mode controller 50 is configured to detect the frequency of the external AC voltage and is configured to reduce the output power of the power converter circuit 1 when the frequency reaches a frequency threshold such as 50.2 Hz or 60.3 Hz that is above a set value, such as 50 Hz or 60 Hz. The frequency of a grid voltage may increase when there is more power input to the grid than there is power consumed by consumers connected to the grid.

The output power of the power converter circuit 1 can be controlled by controlling the input voltages V3 of the individual converter units 2. This has been explained in connection with “START-UP SEQUENCE A” before. The information that a reduction of the output power of the individual converter units 2 is required, may be transmitted from the operation mode controller 50 to the individual converter units 2 through the same channel through which the synchronization signal S_(v1) is transmitted.

Restart

Referring to the explanation above, there may be operation scenarios when the power converter circuit 1 is shut down after an error has occurred. After the power converter circuit 1 has been shut down the power converter circuit can be restarted using one of the start-up sequences explained herein before. In the following, “to restart” the power converter circuit 1 means to employ one of the start-up sequences to again start the power converter circuit 1.

When, e.g., the power converter circuit 1 has been shut down due to an error of the power grid, the operation mode controller 50 can be configured to check the external AC voltage v1 and can be configured to restart the power converter circuit 1 after the grid voltage v1 has returned to normal. The operation mode controller 50 may be configured to check the grid voltage in regular time intervals, such as every minute, every five minutes, etc.

When, e.g., the power converter circuit 1 has been shut down due to an undervoltage condition, due to automatic shutdown, or due to a phase difference, the operation mode controller may be configured to restart the power converter circuit after a given time period, such as, e.g., one minute, two minutes, etc.

Of course, the occurrence of an error may also be detected during start-up so that it is even possible to shut down the power converter circuit 1 before the normal operation mode has been reached.

Referring to explanation before, the output current i1 of the individual converter units 2 may be increased in accordance with a given time profile during the start-up phase. This current profile may be fixed current profile. According to a further embodiment, the profile of the output current i1 during start-up is limited dependent on the shut-down history, which means dependent on whether the power converter circuit 1 has been shut down due to an error. According to one embodiment the output current is increased slower (in accordance with a shallower current profile) when the power converter circuit 1 has been shut down due to an undervoltage condition, due to automatic shutdown, or due to a phase difference. When the restart fails because an error has occurred during the start-up phase, an even shallower current profile may be applied after the next restart. A “shallower current profile” is a profile in which the current increases slower.

In the embodiments explained before, the synchronization signal S_(v1) is provided by the synchronization circuit 10, where the synchronization circuit 10 is configured to generate the synchronization signal S_(v1) dependent on the external AC voltage v1, e.g., in the normal mode, or independent of the external AC voltage, e.g., when an error has occurred.

According to a further embodiment illustrated in FIG. 35, the synchronization circuit 10 includes synchronization units 10 ₁, 10 ₂, 10 _(n) with each synchronization unit 10 ₁, 10 ₂, 10 _(n) coupled to the output terminals of one converter unit 2 ₁, 2 ₂, 2 _(n), configured to measure the output voltage v2 ₁, v2 ₂, v2 _(n) of the corresponding converter unit 2 ₁, 2 ₂, 2 _(n), to generate a synchronization signal dependent on each of the measured output voltages and to provide one synchronization signal to each of the corresponding converter unit 2 ₁, 2 ₂, 2 _(n). According to one embodiment, the individual synchronization signals are proportional to the output voltages v2 ₁, v2 ₂, v2 _(n), so that the individual synchronization units 10 ₁, 10 ₂, 10 ₃ may be implemented as voltage measurement units.

An embodiment of a converter unit 2 that can be used in the power converter circuit 1 of FIG. 35 is illustrated in FIG. 36. The converter unit 2 of FIG. 36 is based on the converter unit 2 explained in detail with reference to FIG. 32. In the converter unit 2 of FIG. 36, the synchronization signal S_(v1) is a voltage measurement signal received by measuring the output voltage v2 of the converter unit 2. The operating principle of the converter unit 2 of FIG. 36 is explained below.

For explanation purposes it is assumed, that the power converter circuit 1 is in the standby mode. In the standby mode, the power converter circuit 1 is connected to the output terminals 11, 12 (see FIG. 35) so that the external AC voltage v1 is applied to the series circuit with the individual converter units 2. In the standby mode, when the output power of the power converter circuit 1 is zero, the output capacitances (C in the converter unit 2 of FIG. 36) of the individual converter units 2 act as a capacitive voltage divider so that the voltages v2 at the outputs of the individual converter units 2 are in phase with the external AC voltage v1. The start-up sequence employed to start up the individual converter units 2 corresponds to start-up sequence B explained before, with the following differences.

At the beginning of the start-up sequence or before the beginning of the start-up sequence, the synchronization signal S_(v1) is provided to the signal generator 20 for a short time period, such as for several periods of the synchronization signal S_(v1), which at this time is a sinusoidal signal that is in phase with the external AC voltage v1. The signal generator 20 synchronizes to the synchronization signal S_(v1) and then autonomously generates the continuous synchronization signal S_(v1)′ in the start-up phase and in the normal mode after the start-up phase. The signal generator 20 can be implemented as explained with reference to FIG. 29 before.

Referring to FIG. 36, the operation mode unit 30 may control the time period when the synchronization signal S_(v1) is provided to the signal generator 20. This is schematically illustrated by having a switch 301 connected between the synchronization unit (not shown in FIG. 36) and the signal generator 20, with the switch being controlled by the operation mode unit. However, this serves to illustrate the operating rather than the implementation. Of course, many different means may be employed to provide the synchronization signal S_(v1) that is dependent on the output voltage v2 to the signal generator for a given time period before or at the beginning of the start-up sequence.

In this converter circuit 1, after the converter circuit 1 has entered the normal mode, the operation mode controller 50 may be configured to detect a phase difference between the output current i1 and the external AC voltage and to shut down the converter circuit 1 when the phase difference exceeds a given threshold. The converter circuit 1 may be shut down as explained before in “TRANSMISSION OF SHUT-DOWN INFORMATION II.” The restart mechanism may correspond to one of the restart mechanisms explained before. At a restart after the shutdown, the converter circuit 1 will again be synchronized to the external voltage v1 as explained before.

According to a further embodiment, the operation mode controller 50 provides a phase shift signal, corresponding to the phase shift signal S_(φ) explained before, to control circuits 5 of the individual converter units 2. In this embodiment, the operation mode controller 50 is configured to adapt the phase shift signal S_(φ) when the phase difference between the output current i_(OUT) and the external voltage v1 is above a first phase difference threshold and below a second phase difference threshold, in order to prevent a further a further increase of the phase difference. Further, the operation mode controller 50 is configured to shut down the converter circuit in order to force a restart when a the phase difference is above the second phase difference threshold.

FIG. 37 illustrates yet another of a topology of a converter unit 2 for generating an AC output voltage v2 from a DC input voltage V3. Like the other converter units explained before, the outputs 23, 24 of the converter unit 2 of FIG. 37 can be connected in series with the output terminals of other corresponding converter units so as to form a power converter circuit 1 explained herein. In FIG. 37, only the topology of one converter 2 unit is shown, control circuits (such as control circuits 5 explained before) are not illustrated.

Referring to FIG. 37, the converter unit 2 includes a first stage 210 that is a combination of an unfolding bridge and a buck converter. The first stage 210 includes two half-bridges each including a first switch 211, 213 and a second switch 212, 214. The first stage 210 further includes a first inductive storage element 215, and a second inductive storage element 216. The first inductive storage element 215 is connected to the output of the first half-bridge, and the second inductive storage element 216 is connected to the output of the second half-bridge, wherein the output of each half-bridge is formed by a circuit node that is common to the first and second switches that form the corresponding half-bridge. The first stage 210 is connected to the input terminals 21, 22 that are configured to receive the supply voltage V3 from a DC power source 3 (not shown in FIG. 37). The switches 211-214 of the two half-bridges can be switched on and off independently of each other by a drive circuit 230 that generates drive signals S211, S212, S213, S214 received by the individual switches 211-214. The operating principle of the first stage 210 is explained further below.

The converter unit 2 further includes a second stage 220 coupled between the inductive storage elements 215, 216 of the first stage and the output terminals 23, 24 of the converter unit 3. The second stage 220, that will also be referred to as boost stage in the following, includes a first switch 221 connected between the first inductive storage element 215 and the first output terminal 23 of the converter stage 2, and a second switch 222 connected between the second output terminal 24 and a circuit node common to the first inductive storage element 215 and the first switch 221. Further, the second inductive storage element 216 is connected to the second output terminal 24. The switches 221, 222 of the second stage can be switched on and off independently of each other by the drive circuit 230 that generates drive signals 5221, 5222 received by the individual switches 221, 222. Referring to FIG. 37 each of the switches 211-214 and 221, 222 of the first and second stage 210, 220 may include a freewheeling diode (that is also illustrated in FIG. 37) connected in parallel with a switching element. In the second stage 220, however, bidirectional blocking and conducting switches are required due to the bipolar nature of the input and output voltage. These bidirectional switches may include two MOSFETs arranged in a back-to-back configuration. Depending on the polarity of the voltage one of the two MOSFETs may be turned on permanently, so that the body diode of the other MOSFET can be used as a freewheeling element that conducts dependent on the polarity of a voltage across the individual switch without requiring a further control signal.

The converter unit 2 is configured to generate the AC output current i1 at the output 23, 24 with a frequency, phase and amplitude as defined by the reference signal S_(REF) received by the drive circuit 230. This reference signal S_(REF) can be generated as explained before.

The operating principle of the converter unit 2 is explained in the following. For explanation purposes it is assumed that the output current i1 to be generated is a sinusoidal current and that the output voltage v2 is a sinusoidal voltage with an amplitude that is higher than the DC input voltage V3. Generating one period of the sinusoidal output voltage v2 includes six phases, namely (A) a first phase in which the instantaneous value of the output voltage v2 is positive and smaller than the input voltage V3; (B) a second phase in which the instantaneous value of the output voltage v2 is positive and higher than the input voltage V3; (C) a third phase in which the instantaneous value of the output voltage v2 is positive and again smaller than the input voltage V3; (D) a fourth phase in which the instantaneous value of the output voltage v2 is negative and has a magnitude that is smaller than the input voltage V3; a fifth phase (E) in which the instantaneous value of the output voltage v2 is negative and has a magnitude that is higher than the input voltage V3; and a sixth phase (F) in which in which the instantaneous value of the output voltage v2 is negative and has again a magnitude that is smaller than the input voltage V3. In the first phase (A), the output current i1 is controlled through the first switch 211 of the first half-bridge that is driven in a PWM fashion by the drive circuit 230. The first switch 221 of the second stage 220 is switched on in this phase, while the second switch 222 of the second stage 220 is switched off. The first switch 213 of the second half-bridge is permanently off in the first phase, and the second switch 214 of the second half-bridge is permanently on. The second switch 212 of the first half-bridge acts as a freewheeling element in those time periods in which the first switch 211 is off. For this, the freewheeling diode takes over the freewheeling current The switch 212 may be turned on parallel to the conducting body diode.

In the first phase (A), the converter unit 2 acts as a buck converter. The amplitude of the output current i1 is controlled through the duty cycle of the first switch 111 in this phase. The amplitude of the output voltage is defined by the external voltage v1 (not shown in FIG. 37).

In the second phase (B), the first switch 211 of the first half-bridge and the second switch 214 of the second half-bridge are on, while the second switch 212 of the first half-bridge and the first switch 213 of the second half-bridge are off. The second switch 222 of the second stage 120 is driven in a PWM fashion, and the first switch 221 acts as a freewheeling element in those time periods when the second switch 122 is off. The amplitude of the output current i1 is controlled through the duty cycle of the second switch 222. In the second phase (B), the converter unit 3 acts as a boost converter, wherein each time the second switch 222 of the second stage 220 is on energy is stored in the first inductive storage element 215. This energy is transferred to the output with the output terminals 23, 24 after the second switch 222 has been switched off.

The operating principle in the third phase (C), corresponds to the operating principle in the first phase (A).

In the fourth phase (D), the output current i1 is controlled through the first switch 213 of the second half-bridge that is driven in a PWM fashion. The first switch 221 of the second stage is on, while the second switch 222 is off in this phase. Further, the first switch 211 of the first half-bridge is off in this phase, the second switch 212 of the first half-bridge is on, and the second switch 214 of the second half-bridge acts as a freewheeling element in those time periods in which the first switch 213 is off. In the fourth phase (D), the converter unit 3 acts as a buck converter providing a negative output current i1. The amplitude of the output current i1 is controlled through the duty cycle of the first switch 213 of the second half-bridge.

In the fifth phase (E), the first switch 213 of the second half-bridge and the second switch 212 of the first half-bridge are on, while the second switch 214 of the second half-bridge and the first switch 211 of the first half-bridge are off. The second switch 222 of the second stage 120 is driven in a PWM fashion, and the first switch 221 acts as a freewheeling element in those time periods when the second switch 222 is off. The amplitude of the output current i1 is controlled through the duty cycle of the second switch 222. In the fifth phase (E), like in the second phase, the converter unit 2 acts as a boost converter.

The operating principle in the sixth phase (F), corresponds to the operating principle in the fourth phase.

The drive circuit 230 may receive an input voltage signal S_(V3) representing the input voltage V3 and an output voltage signal S_(v2) representing the output voltage v2. Based on these signals, the drive circuit 230 detects whether the output voltage v2 is positive or negative, and whether the instantaneous value of the output voltage v2 is higher or lower than the input voltage. Based on this detection, the drive circuit 230 operates the converter unit 2 in one of the buck mode and the boost mode. In each of these phases, the desired level of the output current i1 is defined by the voltage control signal S_(REF). This signal can be an alternating signal in order to generate an alternating output voltage current and can be generated, e.g., dependent on an output current signal S_(i1) and a synchronization signal S_(v1) as explained before. In each case, a switching frequency of those switches that are operated in a PWM fashion is significantly higher than a frequency of the reference signal. The switching frequency can be several 10 kHz or several 100 kHz, while the reference signal can be several 10 Hz, such 50 Hz or 60 Hz. The frequency of the reference signal S_(REF) may vary in order to be able to correctly control the frequency of the output current i1.

In each of the embodiments explained before in which the power converter circuit 1 provides an AC output current to a load, each converter unit 2 provides an AC current io1. For this, each converter unit 2, specifically the DC/AC converter 4 in each converter unit 2, includes an H4 bridge with two half-bridges (see, for example, the H4 bridge with the first half-bridge 42 ₁, 42 ₂ and the second half-bridge 42 ₃, 42 ₄ in FIG. 6).

FIG. 38 illustrates an embodiment of a power converter circuit 1 in which the complexity of the individual converter units 2 can be reduced. In this embodiment, the individual converter units 2 receive a synchronization signal S_(v1″) that is a rectified AC signal instead of an AC signal. Everything else that has been explained in connection with the synchronization signal S_(v1) herein before applies to the synchronization signal S_(v1″) accordingly.

Like the converter units 2 explained before, the converter units 2 of FIG. 38 are configured to generate their output currents i1 with a frequency and phase as defined by the synchronization signal S_(v1″). According to one embodiment, the synchronization circuit 10 generates the synchronization signal S_(v1″) dependent on an external voltage v1 applied to the output terminals 11, 12. Specifically, the synchronization circuit 10 may generate the synchronization signal S_(v1″) such that the synchronization signal S_(v1″) has a frequency and a phase that is dependent on a rectified of the external voltage v1. If, for example, the external voltage v1 has a sinusoidal waveform, then the synchronization signal S_(v1″) has the waveform of a rectified sinusoidal signal. The synchronization signal S_(v1″) may be in phase with the rectified external voltage v1″, or there may be a phase difference between the synchronization signal S_(v1″) and the rectified external voltage v1″.

FIG. 39 schematically shows timing diagrams of an external voltage v1 with a sinusoidal waveform, of the corresponding rectified voltage v1″, and of the synchronization signal S_(v1″). In embodiment illustrated in FIG. 39, the synchronization signal S_(v1″) is in phase with the rectified external voltage v1″. However, this is only an example, it is also possible to have a phase difference between these signals S_(v1″), v1″. FIG. 39 further illustrates a timing diagram of the output current i1 of one of the converter units 2. This output current i1 has a frequency and a phase that is defined by the synchronization signal S_(v1″) so that the output current i1 of one converter unit has the waveform of a rectified sinusoidal signal. In the steady state, an overall output current i_(OUT-REC) of the converter unit series circuit has the waveform of the output currents i1 of the individual converter units 2.

Referring to FIG. 38, an unfolding circuit 300 connected between the series circuit with the converter units and the output terminals 11, 12 receives the output current i_(OUT-REC) provided by the converter unit series circuit and transforms (unfolds) this output current i_(OUT-REC) having the waveform of a rectified AC signal (such as a rectified sinusoidal signal) into an output current i_(OUT) having the waveform of an AC signal (such as a sinusoidal signal). The output current i_(OUT) is output at the output terminals 11, 12.

Referring to FIG. 40, that shows one embodiment of the unfolding circuit 300, the unfolding circuit 330 may include a bridge circuit with two half-bridges similar to the bridge circuit 85 explained with reference to FIG. 19. In FIG. 40, reference character 23 ₁ denotes the first output terminal of the first converter unit 2 ₁ (not shown in FIG. 40), and reference character 23 ₂ denotes the second output terminal of the n-th converter unit 2 _(n) (not shown in FIG. 40). These terminals will be referred to as first and second terminals, respectively, of the converter unit series circuit. The unfolding circuit transforms the series circuit output current i_(OUT-REC) into the AC output current i_(OUT). For this, the unfolding bridge 300 alternatingly assumes a first switching state and a second switching state. In the first switching state, the first terminal 23 ₁ of the series circuit is connected to the first output terminal 11, and the second output terminal 24 _(n) of the series circuit is connected to the second output terminal 12, and in the second switching state, the first terminal 23 ₁ of the series circuit is connected to the second output terminal 12, and the second output terminal 24 _(n) of the series circuit is connected to the first output terminal 12. The unfolding bridge changes the switching state at the beginning of each period of the synchronization signal S_(v1″). In the embodiment of FIG. 38, a new period of the synchronization signal begins each time the synchronization signal S_(v1″) decreases to zero.

Referring to FIG. 40, the unfolding circuit 300 may include a first and a second half-bridge each including a first switch 301, 303 and a second switch 302, 304. In the present embodiment, the two half-bridges are connected between output terminals 23 ₁, 24 _(n) of the converter unit series circuit. An output terminal of the first half-bridge 301, 302 is connected to the first output terminal 11, and an output terminal of the second half-bridge 303, 304 is connected to the second output terminal 12. In this unfolding circuit, the first switch 301 of the first half-bridge and the second switch 304 of the second half-bridge are switched on and the other switches 302, 303 are switched off in the first switching state, and the second switch 302 of the first half-bridge and the first switch 303 of the second half-bridge are switched on and the other switches 301, 304 are switched off in the second switching state. A control circuit 310 receives the synchronization signal S_(v1″) and controls the individual switches such that the unfolding circuit 300 dependent on the synchronization signal S_(v1″) alternatingly assumes the first and second switching states, so as to generate an alternating output current i_(OUT) from the rectified alternating output current i_(OUT-REC) provided by the converter unit series circuit.

According to one embodiment, the synchronization circuit 10 generates the synchronization signal S_(v1″) dependent on the external voltage v1. In this case, the synchronization circuit 10 may receive the external voltage v1 or may receive the rectified external voltage v1″ (as illustrated in dashed lines in FIG. 38). In this embodiment, the control circuit 310 of the unfolding bridge may receive the external voltage v1 (or a signal representing the external voltage) instead of the synchronization signal S_(v1″) in order to control the unfolding bridge. In this embodiment, the control circuit 310 operates the unfolding bridge 300 in the first switching state during positive half-cycles of the external voltage v1, and in the second switching state during negative half-cycles of the external voltage v1.

Referring to FIG. 38, the unfolding bridge 300 not only converts the output current i1 _(OUT-REC) of the series circuit into the output current i1 _(OUT) of the power converter circuit 1, but also converts (rectifies) the external voltage v1 and applies the rectified external voltage v1″ to the series circuit with the converter units 2 (and optionally to the synchronization circuit 10).

According to a further embodiment, the synchronization circuit 10 generates the synchronization signal S_(v1″) based on other information than the external voltage v1. This may become necessary in those cases in which the voltage v1 between the terminals 11, 12 is not an external (grid) voltage, so that it is necessary for the power converter circuit 1 to also define the frequency of this voltage v1. For example, this may become necessary when the power converter circuit 1 operates in an island grid.

In the power converter circuit 1 of FIG. 38, the individual converter units 2 only need to be capable of providing an output current i1 with one polarity and not an output current that periodically changes between a positive and a negative polarity. This allows to simplify the topology of the DC/AC converter 4 in each of the converter units 2. In the context of the present description the term “DC/AC converter” is used in connection with the converters 4 explained before that generate an alternating output current from a direct input current and a direct input voltage, respectively. However, the term “DC/AC converter” is also used in connection with converters that generate an output current with a periodically varying amplitude and with only one polarity, such as an output current having the waveform of a rectified sinusoidal signal.

According to one embodiment, the DC/AC converter 4 in each of the converter units is implemented with a buck converter, a boost-buck converter, or a buck-boost converter topology. One embodiment of a converter unit 2 including a DC/AC converter 4 with a buck topology 4 is illustrated in FIG. 41. Referring to FIG. 41, the DC/AC converter 4 is coupled between the input with the first and second input terminals 21, 22 and the output with the output terminals 23, 24 of the converter unit 2. Optionally, a DC/DC converter 6 is connected between the input 21, 22 of the converter unit 2 and the DC/AC converter 4. This DC/DC converter 6 and the corresponding control circuit 7 may correspond to one of the DC/DC converters 6 explained before.

The DC/AC converter 4 of FIG. 41 can be obtained from one of the DC/AC converters 4 with an H4-bridge explained before by omitting the third switch 42 ₃ and the inductive storage element 44 ₂ and by replacing the fourth switch 42 ₄ by a short circuit. Referring to FIG. 41, the buck converter includes a half-bridge with a high-side switch 401 and a low-side switch 402 connected in series. The half-bridge receives the input voltage V3 or the DC link voltage V6 (when the converter unit 2 includes the DC/DC converter 6). An inductive storage 403 element is coupled between an output of the half-bridge and the output 22, 23 of the converter unit 2. In the present embodiment, the inductive storage element 404 is connected between the output of the half-bridge 401, 402 and the first output terminal 23.

In the DC/AC converter 4 of FIG. 41, the high-side switch 401 is driven in a PWM fashion by a drive circuit 404 such that the output current i1 has a waveform as defined by a reference signal S_(REF) received by the drive circuit 404. The reference signal S_(REF) is generated by the control circuit 5 dependent on the synchronization signal S_(v1″) and an output current signal S_(i1) representing the output current i1. According to one embodiment, the control circuit 5 generates the reference signal S_(REF) such that the DC/AC converter generates the output current i1 to be in phase with the synchronization signal S_(v1″).

In the DC/AC converter 4 of FIG. 41, the low-side switch 402 acts as a freewheeling element that takes over the current through the inductive storage element 403 when the high-side switch 401 is switched off. This low-side switch 402 may include a freewheeling diode (that is also illustrated in FIG. 41). According to one embodiment, the low-side switch 402 is replaced by a freewheeling diode.

The DC/AC converter 4 can be implemented as a buck converter when the level of the output voltage v2 is always smaller than the level of the input voltage V3 and the DC link voltage V60, respectively. If the maximum level of the output voltage v2 of the DC/AC converter is higher than the level of the input voltage V3 and the DC link voltage V60, respectively, the DC/AC converter may be implemented with one of a boost-buck converter topology and a buck-boost converter topology.

One embodiment of a converter unit 2 with a DC/AC converter 4 having a boost-buck converter topology is illustrated in FIG. 42, and one embodiment of a converter unit 2 with a DC/AC converter 4 having a buck-boost converter topology is illustrated in FIG. 43. In FIGS. 42 and 43 an optional DC/DC converter 6 connected between the input terminals 21, 22 and the DC/AC converter 4 is not illustrated. When the converter units of FIGS. 42 and 43 are implemented with a DC/DC converter 6, the DC/AC converter 4 receives the DC link voltage V6 instead of the input voltage V3.

Referring to FIG. 42, the DC/AC converter 4 includes a boost stage with a first inductive storage element 411, first and second switches 412, 413 and a capacitive storage element 414. A series circuit with the first inductive storage element 411 and the first switch 412 receives the input voltage V3. A series circuit with the second switch 413 and the capacitive storage element 414 is connected in parallel with the first switch 412. The boost stage generates a boost voltage V414 across the capacitive storage element 414.

The boost stage operates like a conventional boost converter and may be configured to generate a constant boost voltage V414 at the capacitive storage element 414. In this case, a first drive circuit 418 drives the first and second switches 412, 413 via drive signals S41, S413 such that the boost voltage V414 is constant. For this, the first drive circuit 418 may receive a boost voltage signal S_(V414) representing the boost voltage 414. Specifically, the first drive circuit 418 may drive the first switch 412 in a PWM fashion, wherein energy is stored in the first inductive storage element 411 each time the first switch 412 is switched on. A duty cycle of a PWM drive signal S412 received by the first switch 412 may vary dependent on the boost voltage or, more specifically, dependent on an error between the boost voltage V414 and a desired set-voltage. The second switch 413 acts as a freewheeling element that takes over the current through the inductive storage element 411 and charges the capacitive storage element 414 each time the first switch 412 is switched off.

Referring to FIG. 42, the DC/AC converter 4 further includes a buck stage with a third switch 415, a second switch 416 and a second inductive storage element 417. This buck stage has a topology corresponding to the topology of the DC/AC converter 4 of FIG. 41, wherein the third switch 415 corresponds to the high-side switch 401 of FIG. 41, the fourth switch 416 corresponds to the low-side switch 402 of FIG. 41, and the second inductive storage element 417 corresponds to the inductive storage element 403 of FIG. 41.

A second drive circuit 419 that may correspond to the drive circuit 404 explained with reference to FIG. 41 drives the switches 415, 416 of the buck stage via drive signal S415, S416. In this embodiment, the buck stage is configured to generate an output current i1 with a waveform as defined by the reference signal S_(REF) from the boost voltage V414 provided by the boost stage. Like in the embodiments explained before, the reference signal S_(REF) is output by the control circuit 5.

While in the DC/AC converter 4 of FIG. 42, the boost stage and the buck stage are operated simultaneously, the DC/AC converter 4 with the buck-boost topology illustrated in FIG. 43 either operates as a boost converter (in a boost mode) or operates as a buck converter (in a buck mode). Referring to FIG. 43, the DC/AC converter 4 includes a series circuit with a first switch 421 and a second switch 422 connected between the input terminals 23, 24 and a series circuit with a third switch 423 and a fourth switch 424 connected between the output terminals. An inductive storage element 425 is connected between a first circuit node common to the first and second switches 421, 422 and a second circuit node common to the third and fourth switches 423, 424. This DC/AC converter can be obtained from the converter unit 2 of FIG. 37 by omitting the second half-bridge 213, 214 and the second inductive storage element 216 and by connecting the second input 22 with the second output 24.

A drive circuit 426 controls the individual switches such that the DC/AC converter 4 is either operated in a buck mode or in a boost mode. The operating principle of the DC/AC converter 4 of FIG. 43 corresponds to the operating principle of the converter unit 2 in the operation phases (A) to (C) wherein this converter unit operates in the buck mode in phases (A) and (C) and in the boost mode in phase (B).

When the DC/AC converter of FIG. 43 is in the buck mode, the third switch 423 is permanently on and the fourth switch 424 is permanently off. Further, the first switch 421 is driven in a PWM fashion such that the output current i1 has a waveform as defined by the reference signal S_(REF) received by the drive circuit 426. The second switch 422 acts as a freewheeling element in those time period in which the first switch 421 is switched off. According to one embodiment, the second switch 422 is replaced by a freewheeling element, such as a diode.

In the boost mode, the first switch 421 is permanently switched on and the second switch 422 is permanently switched off. In the boost mode, the control circuit 426 operates the fourth switch 424 in a PWM fashion such that the output current i1 has a waveform as defined by the reference signal S_(REF). The third switch 423 acts as a freewheeling element. Optionally, the third switch 423 is replaced by a diode.

Referring to FIG. 43, the drive circuit 426 besides the reference signal S_(REF) also receives an output voltage signal S_(v2) representing an instantaneous value of the output voltage v2 and an input voltage signal S_(v3) representing the input voltage. The drive circuit 426 is configured to operate the AC/DC converter 4 in the buck mode whenever the output voltage signal S_(v2) and the input voltage signal S_(v3) indicate that the input voltage v3 is higher than the instantaneous value of the output voltage v2. Otherwise, the drive circuit 426 operates the DC/AC converter 4 in the boost mode.

In the embodiments of the power converter 1 circuit explained before, the input terminals 21, 22 of the individual converter units 2 where the DC power sources 3 are connected to are not galvanically isolated from the output terminals 11, 12 where the output current i1 _(OUT) is available. However, especially in those applications in which there is a high ratio between the amplitude of the voltage v1 at the output and the voltages V3 at the inputs a galvanic isolation may be desirable. According to one embodiment a power grid that receives the output current i1 _(OUT) is a middle voltage grid supplying a voltage v1 with an amplitude of between about 10 kV and about 20 kV, while the individual DC power sources 3 output supply voltages of several 10V or several 100V. In this case, a galvanic isolation between the inputs 21, 22 and the output 11, 12 is may be required.

There are several different concepts to provide a galvanic isolation between the inputs 21, 22 and the outputs 11, 12. Two main concepts are explained with reference to FIGS. 44 and 45 below.

FIG. 44 illustrates a first embodiment of a power converter circuit 1 including at least one transformer. In this power converter circuit 1, the individual converter units 2 (reference character “2” denotes an arbitrary one of the converter units 2 ₁-2 _(n) of FIG. 44) each include a DC/DC converter 6 and a DC/AC converter 4 as explained with reference to FIG. 11 herein before. For the ease of illustration, control circuits of the DC/DC converters 6 and the DC/AC converters 4 are not illustrated in FIG. 44. Each of the DC/DC converters 6 is connected between one DC power source 3 and one DC/AC converter 4 and includes a transformer 69 that provides for a galvanic isolation between the DC power source and the output terminals 11, 12. Specific embodiments of the DC/DC converters 6 are explained below.

Although the individual DC/DC converters of FIG. 44 are drawn to include one transformer each, it is also possible that two or more DC/DC converters 6 share one transformer. Each of the DC/DC converters 6 outputs a DC link voltage received by the corresponding DC/AC converter 4.

The individual DC/AC converters 4 can be implemented as explained before. Optionally, an unfolding bridge 300 is connected between the series circuit with the converter units 2 or the series circuit with the DC/AC converters 4, respectively, and the output terminals 11, 12 (as explained with reference to FIG. 38 herein before). The unfolding bridge 300 can be omitted when the individual converter units 2 each output an AC current i1, and the unfolding bridge 300 is connected between the series circuit with the converter units 2 and the output terminals when the individual converter units 2 each output a rectified AC current i1. FIG. 45 illustrates a further embodiment of a power converter circuit 1 including at least one transformer. In this power converter circuit 1, each of the individual converter units 2 includes a DC/AC converter 4, wherein each DC/AC converter 4 includes one transformer 69. Specific embodiments of the DC/AC converters 4 of FIG. 45 are explained with reference to drawings below.

Referring to FIG. 45, the input of each DC/AC converter 4 is coupled to one DC power source 3. Optionally, in each converter unit 2, a DC/DC converter 6 is connected between the DC power source 3 and the DC/AC converter 4. The individual DC/DC converters 6 that each output a DC link voltage V6 may be implemented as explained with reference to FIGS. 12 to 18 herein before. For the ease of illustration, control circuits of the DC/AC converters 4 and the optional DC/DC converters 6 are not illustrated in FIG. 45.

The DC/AC converters 4 can be implemented to either output an AC current i1 or to output a rectified AC current. In the first case, the series circuit with the DC/AC converters 4 can be connected to the output terminals 11, 12, while in the second case an unfolding bridge (illustrated in dashed lines in FIG. 45) receives the rectified AC current and outputs and AC current to the output terminals 11, 12. Specific embodiments of the DC/AC converters 4 are explained with reference to drawings herein below.

Some exemplary embodiments of DC/DC converters 6 that each include a transformer and that may be used in the power converter circuit 1 explained with reference to FIG. 44 are explained with reference to FIGS. 46 to 50 in the following.

FIG. 46 shows a basic topology of a DC/DC converter 6 with a transformer 69 having a primary winding 69 _(P) and a secondary winding 69 _(S). The DC/DC converter 6 includes a switching circuit 621 that receives the input voltage V3 and applies a pulse-width modulated voltage V69 _(P) to the primary winding 69 _(P) of the transformer 69. Optionally, an input capacitor 63 corresponding to the input capacitor 63 explained before is connected between the input terminals 21, 22. The secondary winding 69 _(S) is inductively coupled with the primary winding 69 _(P) and has a rectifier circuit 622 connected thereto. The rectifier circuit 622 includes the DC link capacitor 60 and is configured to generate the DC link voltage V60 from a voltage V69 _(S) across the primary winding. The DC/DC converter 6 can be configured to control at least one of the input voltage V3 and the DC link voltage V60. Just for explanation purposes it is assumed that the DC/DC converter 6 is configured to control the input voltage V3. In this case, the switching circuit 621 receives the input voltage reference signal S_(REF-V3) explained before. An MPP tracker (not shown in FIG. 44) may output the input voltage reference signal S_(REF-V3). The switching circuit 621 can be configured to control the input voltage by suitably adjusting a duty cycle of the PWM voltage V69 _(P) applied to the primary winding 69 _(P).

Optionally, a boost stage 623 (illustrated in dashed lines in FIG. 46) is connected between the input 21, 22 and the switching circuit 621. The boost stage 623 is configured to output a boost voltage V623 that is higher than the input voltage V3 and that is received by the switching circuit 621. The boost stage 623 may include a conventional boost converter topology. In case a boost stage 623 is connected between the input 21, 22 and the switching circuit 621, the boost stage 623 may receive the input voltage reference signal S_(REF-V3) and may be configured to control the input voltage V3.

Four more specific embodiments of DC/DC converters 6 each having a basic topology as explained with reference to FIG. 46 are explained with reference to FIGS. 47 to 50 below. Each of these topologies may include an input capacitor explained with reference to FIG. 46. However, such input capacitor is not illustrated in FIGS. 47 to 50. Further, each of these topologies optionally includes a boost stage connected between the input 21, 22 and the switching circuit 621. However, such boost stage is also not illustrated in FIGS. 47 to 50. FIG. 47 illustrates a first embodiment of a DC/DC converter 6 with a transformer 69 including a primary winding 69 _(P) and a secondary winding 69 _(S). The DC/DC converter 6 of FIG. 47 has a topology known as two transistor forward (TTF) topology. The primary winding 69 _(P) and the secondary winding 69 _(S) have the same winding senses in this type of DC/DC converter 6. The primary winding 69 _(P) is connected between a first switch 506 ₁ and a second switch 506 ₂ of the switching circuit 621, with the series circuit with the switches 506 ₁, 506 ₂ and the primary winding 22 _(P) connected between the input terminals 21, 22 for receiving the DC input voltage V3. A circuit node common to the first switch 506 ₁ and the primary winding 69 _(P) is coupled to the second input terminal 22 via a first rectifier element 507 ₁, such as a diode. Further, a circuit node common to the primary winding 69 _(P) and the second switch 506 ₂ is coupled to the first input terminal 21 via a second rectifier element 507 ₂, such as a diode.

In the rectifier circuit 622, a series circuit with a third rectifier element 504, an inductive storage element 508, and the DC link capacitor 60 is connected in parallel with the secondary winding 69 _(S). The DC link capacitor 60 is connected between the output terminals 61, 62 of the DC/DC converter where the DC link voltage V60 is available. A fourth rectifier element 505 is connected in parallel with the series circuit with inductive storage element 508 and the DC link capacitor 60.

Referring to FIG. 47, a drive circuit 510 generates a drive signal S506 to the first and second switches 506 ₁, 506 ₂ that are synchronously switched on and switched off. The drive signal S506 is a pulse-width modulated (PWM) drive signal with a duty cycle that is dependent on the input voltage reference signal S_(REF-V3) and the input voltage signal S_(V3) representing the input voltage V3. The drive circuit 510 is configured to adjust the duty cycle of the drive signal S506 such that a voltage level of the input voltage V3 corresponds to a voltage level represented by the reference signal S_(REF-V3).

The operating principle of the DC/DC converter 6 of FIG. 47 is as follows. Each time the first and second switches 506 ₁, 506 ₂ are switched on, the primary winding 69 _(P) is connected between the input terminals 21, 22 and a current flows through the primary winding 69 _(P). The polarity of a voltage V69 _(S) across the secondary winding 69 _(S) is as indicated in FIG. 47 when the input voltage V3 has a polarity as indicated in FIG. 47. This voltage causes a current through the third rectifier element 504, the inductive storage element 508 and the DC link capacitor 60. When the switches 506 ₁, 506 ₂ are switched off, the current through the primary winding 69 _(P) continuous to flow by virtue of the two rectifier elements 507 ₁, 507 ₂. However, the polarity of the voltage V69 _(S) across the secondary winding 22 _(S) is inverted, so that a current through the first rectifier element 504 becomes zero and a current induced by the inductive storage element 508 flows through the second rectifier element 505. A temporary increase of the duty cycle of the drive signal S506 at a given input power provided by the DC power source V3 results in an increase of the input current I3 and a decrease of the input voltage V3, and a decrease of the duty cycle results in a decrease of the input current I3 and an increase of the input voltage V3.

In the DC/DC converter 6 of FIG. 47, as well as in other DC/DC converters 6 explained above and below, rectifier elements represented by a diode symbol can be implemented as diodes. However, it is also possible to implement these rectifier elements as synchronous rectifiers (SR) including a switching element, such as a MOSFET.

FIG. 48 illustrates a further embodiment of a DC/DC converter 6. The DC/DC converter 6 of FIG. 48 includes a phase-shift zero-voltage switching (ZVS) full bridge topology. Referring to FIG. 48, the switching circuit 621 includes two half bridges each including a high-side switch 605 ₁, 606 ₁ and a low-side switch 605 ₂, 606 ₂ connected between the input terminals 21, 22 for receiving the input voltage V3. A series circuit with an inductive storage element 610 and the primary winding 69 _(P) of the transformer 69 is connected between output terminals of the two half bridges. The transformer 69 includes a secondary winding with a center tap resulting in two secondary winding sections 69 _(S1), 69 _(S2). Each of the first and second secondary winding sections 69 _(S1), 69 _(S2) is inductively coupled with the primary winding 69 _(P). The primary winding 69 _(P) and the secondary winding 69 _(S1), 69 _(S2) have identical winding senses.

The rectifier circuit 622 includes a series circuit with an inductive storage element 611 and the DC link capacitor 60. The first secondary winding section 69 _(S1) is coupled to this series circuit 611, 60, via a first rectifier element 607, and the second first secondary winding section 69 _(S2) is coupled to the series circuit 611, 60 via a second rectifier element 609. A third rectifier element 612 is connected in parallel with the series circuit with the inductive storage element 611 and the DC link capacitor 60. More precisely, inductive storage element 611 is connected to the first secondary winding section 69 _(S1) via the first rectifier element 607 and to the second secondary winding section 69 _(S2) via the second rectifier element 609. A center tap of the secondary winding 69 _(S1), 69 _(S2) is connected to the circuit node of the DC link capacitor 60 that faces away from inductive storage element 611. This circuit node corresponds to the second output terminal 62.

The switches 605 ₁, 605 ₂, 606 ₁, 606 ₂ of the half-bridges are cyclically switched on and off by a drive circuit 609 dependent on the input voltage reference signal S_(REF-V3) and the input voltage S_(V3) such that the level of the input voltage V3 corresponds to the level represented by the reference signal S_(REF-V3). In FIG. 48, reference characters S605 ₁, S605 ₂, S606 ₁, S606 ₂ denote drive signals provided by the drive circuit 609 to the individual switches 605 ₁, 605 ₂, 606 ₁, 606 ₂. The individual switches 605 ₁, 605 ₂, 606 ₁, 606 ₂ are cyclically switched on and off in accordance with a drive scheme. According to this drive scheme, each cycle includes four different phases. In a first phase, the high-side switch 605 ₁ of the first half-bridge and the low-side switch 606 ₂ of the second half-bridge are switched on. Thus, a current I69 _(P) flows through the first inductive storage element 610 and the primary winding 69 _(P). Voltages V69 _(S1), V69 _(S2) across the secondary winding sections 69 _(S1), 69 _(S2) have polarities as indicated in FIG. 48 when the input voltage V3 has a polarity as indicated in FIG. 48. The voltage V69 _(S1) across the first secondary winding section 69 _(S1) causes a current I607 through the first rectifier element 607, the second inductive storage element 611 and the capacitive storage element 608, while the second rectifier element 609 blocks.

In a second phase, the high side switch 605 ₁ of the first half-bridge is switched on and the high-side switch 606 ₁ of the second half-bridge is switched on. There may be a delay time between switching off the low-side switch 605 ₂ of the first half-bridge and switching on the high-side switch 606 ₁ of the second half-bridge. During this delay time, a freewheeling element (not illustrated) connected in parallel with the high-side switch 606 ₁ may take the current. The switches 605 ₁, 605 ₂, 606 ₁, 606 ₂ may be implemented as power transistors, in particular as power MOSFETs. Power MOSFETs include an integrated body diode that may act as a freewheeling element.

In the second phase, the voltage across the primary winding 69 _(P) and the voltages V69 _(S1), V69 _(S2) across the secondary windings 69 _(S1), 69 _(S2) are zero. The current through the inductive storage element 611 continuous to flow, where the third rectifier element 610 takes over the current through the inductive storage element 611 and the capacitive storage element 608.

In the third phase, the high-side switch 606 ₁ of the second half-bridge and the low-side switch 605 ₂ of the first half-bridge are switched on. The voltages V69 _(S1), V69 _(S2) across the secondary winding sections 69 _(S1), 69 _(S2) have polarities opposite to the polarities indicated in FIG. 11. In this case, a current flows through the second secondary winding section 69 _(S2), the second rectifier element 609, the inductive storage element 611 and the capacitive storage element 608.

In the fourth phase, the low-side switch 605 ₂ of the first half-bridge is switched off, and the half-side switch 605 ₁ of the first half-bridge is switched on. The voltage across the primary winding 69 _(P) and the voltages across the secondary winding sections 69 _(S1), 69 _(S2) turn to zero. The current through the second inductive storage element 611 and the capacitive storage element 608 continuous to flow, where the third rectifier element 609 provides a current path for this current.

According to one embodiment, a timing of switching on and switching off the individual switches 605 ₁, 605 ₂, 606 ₁, 606 ₂ of the two half-bridges is such that at least some of the switches are switched on and/or switched off when the voltage across the respective switch is zero. This is known as zero voltage switching (ZVS).

Like in the DC/DC converters 6 explained before, the input voltage V3 can be controlled such that the level of the input voltage V3 corresponds to the level represented by the reference signal S_(REF-V3). In particular, the input voltage V3 can be regulated by adjusting the time durations of the first phase and the third phase, whereas an increase of these time durations (dependent on the input voltage signal S_(V3) and the reference signal S_(REF-V3)) results in an increase of the input current I3, so that at a given input power provided by the DC power source 3 (not shown in FIG. 48) the input voltage V3 decreases. Equivalently, the input voltage V3 increases when the time durations of the first and third phase increase.

FIG. 49 illustrates a DC/DC converter 6 according to a further embodiment. The DC/DC converter 6 of FIG. 49 is implemented as flyback converter. Referring to FIG. 49, the switching circuit 621 of the DC/DC converter 6 includes a switching element 701 connected in series with the primary winding 69 _(P) of the transformer 69. The series circuit with the primary winding 69 _(P) and the switching element 701 is connected between the input terminals 21, 22 where the input voltage V3 is available. The rectifier circuit 622 that is connected to the secondary winding 69 _(S) of the transformer 69 includes a series circuit with a rectifier element 703 and the DC link capacitor 60. The DC link capacitor 60 is connected between the output terminals 61, 62 of the DC/DC converter 6.

Referring to FIG. 49, the DC/DC converter 6 further includes a drive circuit 702 that is operable to output a PWM drive signal S701 received by the switching element 701.

The basic operating principle of the DC/DC converter 6 is as follows: Each time the switching element 701 is switched on, energy is magnetically stored in the air gap of the transformer 69. The primary winding 69 _(P) and the secondary winding 22 _(S) have opposite winding senses, so that a current through the secondary winding 69 _(S) is zero when the switching element 711 is switched on. When the switching element 711 switches off, the energy stored in the transformer 69 is transferred to the secondary winding 69 _(S) and causes a current from the secondary winding 69 _(S) via the rectifier element 713 to the DC link capacitor 60 of the rectifier circuit 622. Dependent on the specific type of the drive circuit 712, at least one of the operation parameters of DC/DC converter 2 can be adjusted. This is explained in further detail herein below.

According to one embodiment, like in the DC/DC converters 6 explained before, the input voltage V3 is controlled such that the level of the input voltage V3 corresponds to the level represented by the reference signal S_(REF-V3) received by the drive circuit 712. The input voltage V3 can be regulated by adjusting the duty cycle of the PWM drive signal S711, whereas an increase of the duty cycle results in an increase of the input current I3, so that at a given input power provided by the DC power source 3 (not shown in FIG. 47) the input voltage V3 decreases. Equivalently, the input voltage V3 increases when the duty cycle increases.

FIG. 50 illustrates a DC/DC converter 6 according to a further embodiment that includes an LLC resonant topology. Referring to FIG. 50, the switching circuit 621 of the DC/DC converter 6 includes a half-bridge with a high-side switch 805 ₁ and a low-side switch 805 ₂ connected between the input terminals 21, 22 for receiving the DC input voltage V3. The switching circuit 621 further includes a series LLC circuit with a capacitive storage element 806, an inductive storage element 807, and the primary winding 69 _(P) of the transformer 69. This series LLC circuit is connected in parallel with the low-side switch 805 ₂. A further inductive storage element 808 is connected in parallel with the primary winding 69 _(P).

The transformer 69 includes a center tap resulting in two secondary winding sections, namely a first secondary winding section 69 _(S1) and a second secondary winding section 69 _(S2) coupled to the primary winding 69 _(P) and each having the same winding sense as the primary winding 69 _(P). In the rectifier circuit 622, the first secondary winding section 69 _(S1) is coupled to the first output terminal 61 through a first rectifier element 809, and the second secondary winding section 69 _(S2) is coupled to the first output terminal 61 through a second rectifier element 810. A circuit node common to the first and second secondary winding sections 69 _(S1), 69 _(S2) is coupled to the second output terminal 62. The DC link capacitor 60 is connected between the output terminals 61, 62. The DC link voltage V6 is available between the output terminals 61, 62.

In FIG. 50, reference characters S805 ₁, S805 ₂ denote drive signals received by the switches 805 ₁, 805 ₂ of the half-bridge. These drive signals S805 ₁, S805 ₂ are generated by a drive circuit 812 in accordance with the input voltage signal S_(V3) and the reference signal S_(REF-V3) such that the level of the input voltage V3 corresponds to a level represented by the reference signal S_(REF-V3).

The operating principle of the DC/DC converter of FIG. 50 is as follows. The drive circuit 812 alternatingly switches the high-side switch 805 ₁ and the low-side switch 805 ₂ on and off. This causes an alternating current through the primary winding 69 _(P) of the transformer 69. This alternating current is transferred to the secondary side. When the alternating current through the primary winding 69 _(P) has a first direction, a current on the secondary side flows through the first secondary winding section 69 _(S1) and the first rectifier element 809 to the DC link capacitor 60 and the output terminals 61, 62, respectively. When the current through the primary winding 69 _(P), has an opposite second direction, the current on the secondary side flows through the second secondary winding section 69 _(S2) and the second rectifier element 810 to the DC link capacitor 60 and the output terminals 61, 62, respectively.

The series LLC circuit has two resonance frequencies, namely a first resonance frequency, and a second resonance frequency lower than the first resonance frequency. In order to control the input power of the DC/DC converter 6 (and to thereby control the input voltage V3) the drive circuit 812 operates the first and second switches 805 ₁, 805 ₂ with a frequency that is typically between the first and the second resonance frequency and close to the first resonance frequency, wherein through a variation of the switching frequency the quality factor of the LLC circuit can be varied. By varying the quality factor the input power and, therefore, the input voltage V3 of the DC/DC converter 6 can be adjusted.

Although a TTF topology, a phase-shift ZVS topology, a flyback topology, and a half-bridge LLC topology have been explained in detail, the implementation of the DC/DC converters 6 is not restricted to these topologies. Other conventional DC/DC converter topologies including a transformer, such as a single transistor forward topology, a full-bridge LLC topology, or an active clamp forward topology may be used as well. These topologies are commonly known, so that no further explanations are required in this regard. Further, the individual DC/DC converters 6 could be implemented as interleaved DC/DC converters. An interleaved DC/DC converter includes at least two of the topologies explained herein, wherein these topologies are connected in parallel so as to commonly receive the DC input voltage V3, wherein the individual topologies connected in parallel are activated in a timely interleaved fashion.

In the embodiment of FIG. 44, each converter unit 2 receives a DC voltage V3 from a DC power source 3. The level of the DC voltage V3 is dependent on the specific type of DC power source. According to one embodiment, the individual DC power sources 3 each include a string with several PV modules connected in series, so as to provide a voltage level of between several 10V and several 100V. In this case, the power converter circuit 1 can be configured to be coupled to a mid-voltage grid supplying voltages of between 10 kV and 20 kV.

In case the individual DC/AC converters 4 are configured to generate a rectified AC current i1, an unfolding bridge 300 is connected between the series circuit with the DC/AC converters 4 and the output 11, 12 as explained with reference to FIG. 44. The topology of the unfolding bridge 300 may correspond to the topology of the unfolding bridge 300 of FIG. 40, wherein the individual switches 301-304 are selected such that they are capable to withstand the voltage between the output terminals 11, 12. According to one embodiment, these switches 301-304are implemented as thyristors.

A power converter circuit 1 configured to be coupled to a mid-voltage grid, may include converter units 2 with any of the topologies explained with reference to FIGS. 46 to 50 herein before. According to one specific embodiment, each converter unit 2 includes a DC/DC converter 2 with boost stage 623 (see FIG. 46) and with a PS-ZVS converter explained with reference to FIG. 48. A ratio between the input voltage V3 and the boost voltage V623 (see FIG. 46) provided by the boost stage 623 is, e.g., between 1.2:1 and 10:1. Referring to the concept explained with reference to FIG. 45, the DC/AC converters 4 in the individual converter units 2 provide for a galvanic isolation between the inputs 21, 22 where the DC power sources 3 are connected thereto and the output 11,12. That is, each of the DC/AC converters 4 explained before can be replaced by a DC/AC converter 4 comprising a transformer.

For example, in the embodiment of FIG. 19, the converter 80 with the buck converter topology could be replaced by a converter 80 with a flyback converter topology including a transformer. A DC/AC converter 4 modified in this way is illustrated in FIG. 51. In this embodiment, the DC/AC converter 4 is connected to the input terminals 21, 22 that receive the DC input voltage V3. However, as explained with reference to FIG. 45, it is also possible to connect a DC/DC converter 6 between the input terminals 21, 22 and the DC/AC converter 4. In this case, the DC/AC converter 4 receives the DC link voltage V6 (not shown in FIG. 51) instead of the input voltage V3.

The converter 80 of FIG. 51 includes a conventional flyback converter topology including a series circuit with a primary winding 84 _(P) of a transformer and a switching element 83 coupled to the input terminals 21, 22. Further, a rectifier circuit with a rectifier element 86 and optional output capacitor 89 is connected to a secondary winding 84 _(S) of the transformer. The secondary winding 84 _(S) is inductively coupled with the primary winding 84 _(P).

The operating principle of the converter 80 of FIG. 51 corresponds to the operating principle of the converter 80 of FIG. 19. That is, the switch 83 receives a PWM drive signal from the drive circuit 87 such that a signal waveform of the output current i80 of the converter 80 has a waveform as defined by the reference signal S_(REF) received by the drive circuit 87. The control circuit 5 generates the reference signal S_(REF) dependent on the synchronization signal S_(v1) and the output current signal S_(i1) such that there is a predefined phase difference between the output current and the synchronization signal S_(v1). The converter 80 generates the output current i80 to have the waveform of a rectified alternating current.

The other features of the converter unit 2 of FIG. 51 correspond to the converter unit 2 explained with reference to FIG. 19. That is, an unfolding bridge 85 receives the output current i80 from the converter 80 and generates an alternating output current i1 from the rectified alternating current i80.

In a power converter circuit implemented with a plurality of converter units 2 as illustrated in FIG. 51, each converter unit 2 has an unfolding bridge 85. However, in accordance with the embodiment explained with reference to FIG. 38 and as explained with reference to FIG. 45, it is also possible to implement each of the individual converter units 2 with the converter 80 only and to provide only one unfolding bridge (300 in FIG. 38) for one series circuit with a plurality of converter units 2. This is equivalent to implementing the converter units 2 ₁-2 _(n) each with a flyback converter corresponding to the flyback converter 80 of FIG. 51.

However, implementing the converter 80 with a flyback converter topology is only an example. This converter 80 could be implemented with another converter topology including a transformer explained before. According to a further embodiment (not illustrated), the individual DC/AC converter 4 have a cycloinverter topology as disclosed in Trubitsyn, et al., “High-Efficiency Inverter for Photovoltaic Applications,” IEEE, Energy Conversion Congress and Exposition (ECCE), 2010, pages 2803-2810.

FIG. 52 illustrates yet a further embodiment of a power converter circuit 1. This power converter circuit 1 includes a DC/DC stage with a plurality of DC/DC converters that share one transformer 69. In the present embodiment, the transformer 69 includes m primary windings 69 _(P1)-60 _(Pm) and n secondary windings 69 _(S1)-60 _(Sn) that are inductively coupled. Each of the primary windings 69 _(P1)-60 _(Pm) is coupled to a switching circuit 621 ₁-621 _(m), wherein each of the switching circuits 621 ₁-621 _(m) is connected to an input with input terminals 21 ₁, 21 _(m), 22 ₁, 22 _(m). In the present embodiment, each of the switching circuits 621 ₁, 621 _(m) is connected to a different DC power source. However, this is only an example. According to a further embodiment (not illustrated) two or more switching circuits are connected to one common DC power source. Referring to FIG. 50, a rectifier circuit 622 ₁-622 _(n) is connected to each of the secondary windings 69 _(S1)-69 _(Sn). Each rectifier circuit 622 ₁-622 _(n) is configured to generate a DC link voltage V6 ₁-V6 _(n) from a voltage across the corresponding secondary winding 69 _(S1)-69 _(Sn). Each of a plurality DC/AC converters 4 ₁-4 _(n) that have their outputs connected in series receives one of the DC link voltages V6 ₁-V6 _(n), wherein the individual DC/AC converters 4 ₁-4 _(n) together output the output current i1. Optionally, an unfolding bridge 300 is connected between the series circuit with the DC/AC converters 4 ₁-4 _(n) and the output terminals 11,12.

In the present embodiment, the number m of switching circuits 621 ₁-621 _(m) and the number of rectifying circuits 622 ₁-622 _(n) are not equal, wherein m<n. However, it is also possible the implement the power converter circuit 2 with the same number of switching circuits 621 ₁-621 _(m) and rectifying circuits 622 ₁-622 _(n) (m=n), or with less rectifying circuits 622 ₁-622 _(n) than switching circuits 621 ₁-621 _(m) (m>n).

The individual DC/AC converters 4 ₁-4 _(n) can be implemented with one of the DC/AC converter topologies explained herein. The control scheme of the DC/AC converters 4 may correspond to the control schemes explained above.

In the power converter arrangement of FIG. 50, each of the switching circuits 621 ₁-621 _(m) forms a DC/DC converter with one of the rectifier circuit 622 ₁-622 _(n). The individual switching circuits 621 ₁-621 _(m) and the corresponding rectifier circuits 622 ₁-622 _(n) can be implemented with one of the topologies explained with reference to FIGS. 47 to 50 before, wherein the topology of the individual rectifier circuits 622 ₁-622 _(n) is adapted to the topology of the switching circuits 621 ₁-621 _(m). That is, the switching circuits 621 ₁-621 _(m) have a topology according to one DC/DC converter topology explained before, and the rectifier circuit have a topology according to the same DC/DC converter topology.

FIG. 53 illustrates a further embodiment of a power converter circuit 1 including a plurality of converter units 2 having their outputs 23, 24 connected in series between output terminals 11, 12 of the power converter circuit 1. The individual converter units 2 can be implemented as explained with reference to FIGS. 5 to 36 herein before and each include a DC/AC converter 4. Optionally, a DC/DC converter 6 is connected between the input 21, 22 of the individual converter unit 2 and the corresponding DC/AC converter. Referring to the explanation above, each of the DC/AC converters 4 outputs an AC current i1 in accordance with the synchronization signal S_(V1). The frequency of the AC currents is, e.g., 50 Hz or 60 Hz and is defined by the synchronization signal S_(V1).

In order to provide for a galvanic isolation between the inputs 21, 22 of the individual converter units 2 and the output 11, 12 of the power converter circuit 1, each converter unit 2 additionally to the DC/AC converter 4 and the optional DC/DC converter 2 includes a transformer 69 with a primary winding coupled to the output of the corresponding DC/AC converter 4 with a secondary winding. The secondary windings of the individual transformers 69 are connected in series between the output terminals 11, 12 of the power converter circuit 1. The transformers 69 are low frequency transformers that are capable to generate a secondary side current (that is a current through the secondary winding) that corresponds to a primary side current (that is a current through the primary winding) or that is proportional to the primary side current. In each case, the primary side current is the current output by the corresponding DC/AC converter.

Although an operation mode controller 50, a connection circuit 70 and a measurement circuit 600 is only illustrated in the power converter circuits 1 of FIGS. 31 and 35, an operation mode controller 50, a connection circuit 70 and a measurement circuit 600 could be implemented in each of the other power converter circuits 1 explained herein before as well.

Each of the circuits explained before may be implemented as analog or digital circuit, or as a mixed circuit with analog and digital circuit means. Consequently, the signals explained before may be analog or digital signals. In case of the synchronization signal S_(v1) or S_(v1)′, respectively, “continuous synchronization signal” means that the synchronization signal is available in each period of the AC output current i1 and has a waveform corresponding to the waveform of the corresponding output current i1. FIG. 54 illustrates a further embodiment of a converter unit 2 that may be used in one of the power converter circuits explained herein before. This converter unit 2 includes a DC/AC converter 4. The converter unit 2 may further include a DC/DC converter 6 (illustrated in dashed lines in FIG. 54) connected between the input terminals 21, 22 of the converter unit 2 and the DC/AC converter 4. The optional DC/DC converter 6 can be implemented in accordance with one of the embodiments explained herein before and can include one of a non-isolating topology (e.g., as disclosed in FIG. 12, 14, or 16), and an isolating topology including a transformer (e.g., as disclosed in FIGS. 44, 47, 48, 49, 50 and 52). Dependent on whether or not the converter unit 2 includes the DC/DC converter 6 the DC/AC converter 4 either receives the input voltage V3 from the DC power source 3 (not shown in FIG. 54), or the output voltage of the DC/DC converter 6 as an input voltage V4. This input voltage V4 is, in particular, a direct voltage (DC voltage).

The DC/AC converter 4 depicted in FIG. 54 is based on the DC/AC converter 4 depicted in FIG. 19 to which reference is made. Like the DC/AC converter according to FIG. 19, the DC/AC converter according to FIG. 54 includes a converter stage 80 that is configured to generate an output current i80 at an output 81, 82 in accordance with the reference signal S_(REF). This output current i80 is a rectified version of the output current i1 of the DC/AC converter 4. If, for example, a desired waveform of the output current i1 is a sinusoidal waveform, then the output current i80 of the converter stage 80 is generated in accordance with the reference signal S_(REF) such that it has the waveform of a rectified sinusoidal curve (a waveform representing the magnitude of a sinusoidal curve). The reference signal S_(REF) can be generated in accordance with one of the embodiments disclosed herein before in which a reference signal having a waveform of a rectified alternating signal is provided.

Referring to FIG. 54, the converter stage 80 is implemented with an inverting buck boost topology. The input voltage V4 received at an input of the converter stage 80 and the output voltage v80 provided at the output 81, 82 of the converter stage 80 are referenced to the first output node 81 and have opposite polarities. This is different from the converter stage 80 shown in FIG. 19 in which the input voltage V3 and the output voltage v80 are referenced to the second output mode 82 and have the same polarity. The output current i80 of the converter stage 80 shown in FIG. 54 has a current flow direction opposite to the directions indicated by arrows in FIG. 54.

FIG. 55 schematically illustrates timing diagrams of the input voltage V4, the output current i80, and the output voltage v80 of the converter stage 80, and the reference signal S_(REF). Basically, the waveforms illustrated in FIG. 55 correspond to the waveforms illustrated in FIG. 20, with the difference that the output voltages v80 in the embodiments shown in FIGS. 19 and 54 have opposite polarities, and the output currents i80 in the embodiments shown in FIGS. 19 and 54 have opposite polarities.

Referring to FIG. 54, an unfolding bridge 85 that can be implemented in accordance with the embodiment shown in FIG. 19 receives the output current i80 and the output voltage v80 from the converter stage 80 and supplies the output current i1 and the output voltage v2 to the output 23, 24 of the converter unit 2, and the DC/AC converter 4, respectively. Optionally, an EMI filter 88 is coupled between the unfolding bridge 85 and the output 23, 24. This EMI filter can be implemented in accordance with the embodiment shown in FIG. 19.

Like the unfolding bridge 85 explained with reference to FIG. 19, the unfolding bridge 85 shown in FIG. 54 is configured to be operated in one of two different operation states. In a first operation state, the unfolding bridge 85 passes the output current i80 and the output voltage v80 through to the output 23, 24, or the EMI filter 88, respectively, and in a second operation state the unfolding bridge 85 inverts the output current i80, and the output voltage v80, respectively. Referring to the embodiment shown in FIG. 19, the first operation state can be obtained by switching on the first switch 85 ₁ and the fourth switch 85 ₄, and by switching off the second switch 85 ₂, and the third switch 85 ₃. The second operation state can be obtained by switching on the second switch 85 ₂ and the third switch 85 ₃, and by switching off the first switch 85 ₁ and the fourth switch 85 ₄. The unfolding bridge 85 is driven by the drive circuit 89, and changes the operation state at the beginning of each cycle on the output current i80, and the output voltage v80, respectively. A cycle of the output current i80, and the output voltage v80, respectively, begins when the magnitude of the output current i80, and the output voltage v80, respectively, has decreased substantially to zero and begins to increase.

Referring to FIG. 54, the converter stage 80 includes a series circuit with an inductive element 84, such as a choke, and a switch 83. The series circuit with the inductive element 84 and the switch 83 receives the input voltage V4. A rectifier element 86, such as a diode, is coupled between a circuit node common to the inductive element 84 and the switch 83 and the second output node 82 of the converter stage 80. A circuit node of the inductive element 84 facing away from the switch 83 and the rectifier element 86 is coupled to the first output node 81 of the converter stage 80. Optionally, an output capacitor 89 is coupled between the first and second output nodes 81, 82, and an input capacitor is coupled between input nodes which receive the input voltage V4.

The switch 83 of the converter stage 80 receives a drive signal S83 from a drive circuit 87. This drive signal S83 switches on or switches off the switch 83, and is generated by a drive circuit 87 dependent on an output current signal S_(i80) representing the output current i80, and the reference signal S_(REF) such that a waveform of the output current i80 is in correspondence with a waveform of the reference signal S_(REF). That is, the output current i80 has a frequency and a phase as defined by the reference signal S_(REF). According to one embodiment, a switching frequency of the drive signal S83 is significantly higher than a frequency defined by the reference signal S_(REF), and the output current i80, respectively. According to one embodiment, a frequency defined by the reference signal S_(REF) is 100 Hz or 120 Hz, while a switching frequency of the drive signal S83 is several 10 kHz, several 100 kHz, or even several MHz. The frequency and phase information included in the reference signal is dependent on the frequency and phase information included in the synchronization signal S_(v1) received by the drive circuit 87. While, according to one embodiment, the reference signal S_(REF) is a continuous signal, the synchronization signal, as explained with reference to exemplary embodiments herein before, can be a continuous or a discontinuous signal.

One way of operation of the converter stage shown in FIG. 54 is explained in the following. When the drive signal S83 switches on the switch 83, a current I84, driven by the input voltage V4, flows through the inductive element 84 and the switch 83 in a direction as indicated by an arrow in FIG. 54. In this way, energy is magnetically stored in the inductive element 84. When the drive signal S83 switches off the switch 83, the energy stored in the inductive element 84 causes the current I84 through the inductive element to continue, wherein the current I84 then flows through the rectifier element 86, via the output nodes 82, 81 and the optional output capacitor 89.

FIG. 56 schematically shows timing diagrams of the drive signal S83, the current I84 through the inductive element 84, and an a current i80′ into a circuit node common to the output capacitor 89 and one of the output nodes 81, 82 in two subsequent drive cycles, wherein each drive cycle includes an on-period, in which the drive signal S83 has an on-level that switches on the switch 83, and an off-period in which the drive signal S83 has an off-level that switches off the switch 83. Just for the purpose of explanation it is assumed that the on-level of the drive signal S83 is a high-level, and the off-level of the drive signal S83 is a low-level. Referring to FIG. 56, the converter stage 80 can be operated in a continuous current mode (CCM). In this operation mode, a new drive cycle starts before the current I84 through the inductive element 84 has decreased to zero, that is, before the inductive element 84 has been demagnetized. Referring to FIG. 56, the current through the inductive element I84 increases during the on-period, and decreases during the off-period. The current i80′ corresponds to the current through the inductive element 84 during the off-periods.

The output capacitor (low pass) filters the (discontinuous) current i80′ and provides the output current i80 of the converter. In particular, the output capacitor 89 filters out ripples resulting from the switched-mode operation of the switch 83. However, the output capacitor 89 does not significantly affect the desired low frequency waveform of the output current i80 that is defined by the synchronization signal S_(v1) and the reference signal S_(REF), respectively.

The drive signal S83 can be pulse-width modulated (PWM) signal with a fixed frequency, that is with a fixed duration T of one drive cycle (with T=T_(ON)+T_(OFF), where T_(ON) is the duration of the on-period, and T_(OFF) is the duration of the off-period). In this case, the magnitude of the current I84 through the inductive element 84 and, therefore, the magnitude of the output current i80 can be varied by varying the duty cycle of the drive signal S83, wherein the magnitude increases when the duty cycle (temporarily) increases, and decreases when the duty cycle (temporarily) decreases. The drive circuit 87 is configured to vary the duty cycle of the drive signal S83 such that the output current and, more precisely, the average of the output current i80 in each drive cycle has a waveform as defined by the reference signal S_(REF).

Unlike the converter stage with the buck topology illustrated in FIG. 19, the converter stage 80 with the inverting buck boost topology shown in FIG. 54 is capable of supplying the output voltage v80 with a voltage level that is below a voltage level of the input voltage V4, and with a voltage level that is above a voltage level of the input voltage V4. The voltage level of the output voltage v80 is defined by the output current that is controlled dependent on the reference signal S_(REF).

FIG. 57 illustrates a modification of the converter stage 80 shown in FIG. 54. In the embodiment shown in FIG. 57, the rectifier element 86 is an active rectifier element that includes a switch 86 ₁, in particular, an electronic switch. Optionally, a passive rectifier element, such as a diode, is connected in parallel with the switch 86 ₁. The switch 86 ₁ of the active rectifier element 86 is driven by a drive signal S86 generated by the drive circuit 87. One way of driving this switch is explained in further detail herein.

The switch 83 that is driven by the drive signal S83 can be implemented as a conventional electronic switch, such as a MOSFET, IGBT or a GaN-HEMT. Just for the purpose of explanation, it is assumed that the electronic switch 83 is a MOSFET, specifically an n-type MOSFET. Referring to FIG. 57, the electronic switch includes an output capacitance C83 in parallel with an internal load path (which is a drain-source path in the MOSFET). This output capacitance C83 is charged when the electronic switch 83 switches off. In the converter stage 80 illustrated in FIG. 57, a voltage V83 across the output capacitance C83 in the off-state of the electronic switch 83 is: V83=V3−v80 (when a voltage across the rectifier element 86 is neglected). Since the input voltage V4 and the output voltage v80 have opposite polarities, the magnitude of the voltage V83 across the output capacitance C83 corresponds to the magnitude of the input voltage V3 plus the magnitude of the output voltage v80.

The output capacitance C83 is discharged when the electronic switch 83 switches on. Charging the output capacitance C83 when the electronic switch 83 switches off, and discharging the output capacitance C83 when the electronic switch 83 switches on, causes losses (that can be referred to as capacitive switching losses). The converter stage illustrated in FIG. 57 can be operated as explained with reference to FIG. 56, wherein the switch 56 ₁ of the active rectifier element 56 is switched on when the switch 83 switches off, and is switched off when the switch 83 switches on.

FIG. 58 shows timing diagrams that illustrate an operation mode of the converter stage 80 shown in FIG. 57 in which capacitive switching losses can be reduced. FIG. 58 shows timing diagrams of the current I84 through the inductive element 84, the drive signal S83 of the switch 83, and the drive signal S86 of the active rectifier element 86. Just for the purpose of explanation it is assumed that a high-level of the drive signal S86 switches on the switch 86 ₁ of the active rectifier element 86, and a low-level of the drive signal S86 switches off the switch 86 ₁ of the active rectifier element 86.

Referring to FIG. 58, one drive cycle includes an on-period in which the switch 83 is switched on, and a subsequent off-period in which the switch 83 is switched off. Further, one drive cycle includes four different phases I-IV.

In a first phase I, the electronic switch 83 is switched on and the switch of the active rectifier element 86 is switched off. In this first phase I, that corresponds to the on-period, the current I84 through inductive element 84 increases.

A second phase II, begins when the electronic switch 83 switches off and the active rectifier element 56 takes over the current from the inductive element 84. According to one embodiment, the switch 86 ₁ of the active rectifier element 86 switches on when the switch 83 switches off. According to another embodiment, the active rectifier element 86 includes the switch 86 ₁ and the passive rectifier element 86 ₂, and there is a dead time between switching off the electronic switch 83 and switching on the switch of the active rectifier element 86, so that the passive rectifier element 86 ₂ takes over the current during the dead time. According to one embodiment, the active rectifier element 86 is implemented as a MOSFET with an integrated body diode, wherein the body diode acts as the passive rectifier element in this case.

Referring to FIG. 58, the current I84 through the inductive element 84 decreases during the second phase II. A third phase III begins when the current I84 has decreased to zero, that is, when the inductive element 84 has been completely demagnetized. At this time, the current I84 through the inductive element 84 changes its current flow direction, wherein this current I84 is supplied by the energy stored in the output capacitor 89. In this third phase III, the switch 86 ₁ of the active rectifier element 86 is switched on.

The switch 86 ₁ of the active rectifier element 86 is switched off at the end of the third phase III and the beginning of a fourth phase IV. During this fourth phase IV, the current I84 through the inductive element 84 continues, where the current in this phase IV flows through the inductive element 84, the output capacitance C83 of the electronic switch 83 and the input 21, 22 and discharges the output capacitance C83 of the electronic switch 83. The output capacitance C83 has been completely discharged when the voltage V83 across the output capacitance is substantially zero. At this time the electronic switch 83 is again switched on, so that a new drive cycle starts. According to one embodiment, a duration of the third phase III is selected such that the current I84 through the inductive element 84 is substantially zero at the time when voltage V83 across the output capacitor C83 is substantially zero. According to a further embodiment, the duration of the third phase III is longer than in the embodiment disclosed before so that that there is still a current I84 flowing through the inductive element 84 at the time the voltage across the output capacitor C83 has decreased to zero.

In the operation mode explained with reference to FIG. 58, the electronic switch 83 switches on when the voltage across the electronic switch 83 is substantially zero, so that capacitive switching losses can be very low.

FIG. 59 illustrates a further embodiment of a converter unit 2. This converter unit is based on the converter unit 2 illustrated in FIG. 54 and is different from the converter unit illustrated in FIG. 54 in that the unfolding bridge 85 is missing. This converter unit 2 may be employed in a power converter circuit as illustrated in FIG. 38 that includes one central unfolding bridge. The operation of the converter stage 80 of the converter unit 2 shown in FIG. 59 corresponds to the operation of the converter stage 80 shown in FIG. 54. The converter stage 80 shown in FIG. 59 may be modified as explained with reference to FIGS. 57 and 58.

The embodiments explained hereinbefore relate to a single phase power converter circuit, which is a power converter circuit configured to supply a single phase output current i_(OUT) via the output 11, 12 into a single phase power grid. However, the concept of connecting a plurality of converter units 2 ₁-2 _(n) in series, wherein each converter unit is configured to supply an alternating output current in accordance with a synchronization signal S_(v1) is not restricted to be used in a single phase power converter circuit but may also be used in a multi-phase power converter circuit, such as a 3-phase power converter circuit.

FIG. 60 schematically illustrates one embodiment of a 3-phase power converter circuit. This 3-phase power converter circuit includes three single phase power converter circuits 1 _(R), 1 _(S), 1 _(T), wherein each of these single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) can be implemented like the single phase power converter circuit explained herein before. In FIG. 60, one single phase power converter circuit 1 _(R) of these three single power converter circuits is illustrated in detail, the other two single phase power converter circuits 1 _(S), 1 _(T) are only schematically illustrated. The topology of the single phase converter 1 _(R) shown in FIG. 60 corresponds to the topology of the single phase power converter circuit shown in FIG. 1 to which reference is made. Instead of the topology shown in FIG. 1, the topology shown in FIG. 23 may be used in the single phase converter 1 _(R) as well. In the single phase converter 1 _(R) shown in FIG. 60 and the single phase converter 1 shown in FIG. 1, like features have corresponding reference characters, wherein the reference characters in FIG. 60 additionally include an index “R.” For example, the power converter units in the single phase converter 1 shown in FIG. 1 have reference characters 2 ₁-2 _(n), while the corresponding power converter units in the single phase converter 1 _(R) shown in FIG. 60 have reference characters 2 _(R1)-2 _(Rn). The individual converter units 2 _(R1)-2 _(Rn) of the single phase converter 1 _(R) shown in FIG. 60 can be implemented in accordance with one of the embodiments explained herein before.

The 3-phase power converter circuit is configured to be coupled to a 3-phase power grid. This 3-phase power grid may include three phases R, S, T and a neutral N as illustrated in FIG. 60 (where the three phases R, S, T and the neutral N are schematically illustrated). Referring to FIG. 61, the 3-phase power grid may include three phases R, S, T, only.

Referring to FIG. 60, each of the three single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) includes an output, with each of these outputs including two output nodes 11 _(R), 12 _(R), 11 _(S), 12 _(S), and 11 _(T), 12 _(T), respectively. Each of the single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) is configured to be coupled to one of the three phases R, S, T and the neutral N. For this, a first output terminal 11 _(R) of a first single phase power converter circuit 1 _(R) is coupled to a first phase R, a first output terminal 11 _(S) of a second single phase power converter circuit 1 _(S) is coupled to a second phase S, and a first output terminal 11 _(T) of a third single phase power converter circuit 1 _(T) is coupled to a third phase T. Second output terminals 12 _(R), 12 _(S), 12 _(T) of the individual single phase power converter circuits 1 _(R), 1 _(S), 1 _(T), are coupled to the neutral N.

Each of the three single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) supplies an output current i1 _(ROUT), i1 _(SOUT), i1 _(TOUT) to the corresponding phase, wherein the corresponding output current i1 _(ROUT), i1 _(SOUT), i1 _(TOUT) is generated dependent on a synchronization signal in the way explained herein before. Each of the three single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) includes a synchronization circuit (only synchronization circuit 10 _(R) of power converter circuit 1 _(R) is shown in FIG. 60) that provides a synchronization signal (only synchronization signal S_(Rv1) of synchronization circuit 10 _(R) is shown in FIG. 60) to the series-connected converter unit in the individual single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) (in FIG. 60, only power converter units 2 _(R1), 2 _(R2), 2 _(Rn) of the single phase power converter circuit 1 _(R) are shown). The synchronization signals in the individual power converter circuit 1 _(R), 1 _(S), 1 _(T) can be generated in the way explained herein before, for example, by measuring the corresponding phase voltage v1 _(R), v1 _(S), v1 _(T) and generating the synchronization signal dependent on the measured phase voltage v1 _(R), v1 _(S), v1 _(T). In the embodiment shown in FIG. 60 each phase voltage v1 _(R), v1 _(S), v1 _(T) is a voltage between one of the phases R, S, T and the neutral N. In a conventional 3-phase power grid, these phase voltages v1 _(R), v1 _(S), v1 _(T) are sinusoidal voltages with about 220V_(RMS) or 110V_(RMS) and a phase difference of 120° between two phase voltages.

According to one embodiment, the output currents i1 _(ROUT), i1 _(SOUT), i1 _(TOUT) are generated to be alternating currents, such as sinusoidal currents, with the same frequency but different phases. According to one embodiment, a phase difference between these output currents i1 _(ROUT), i1 _(SOUT), i1 _(TOUT) is 120°. Timing diagrams of sinusoidal output currents i1 _(ROUT), i1 _(SOUT), i1 _(TOUT) with a phase difference of 120° are schematical illustrated in FIG. 62. These currents are suitable to be fed into a 3-phase power grid of the kind explained before and illustrated in FIG. 60.

The individual single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) can be implemented identically, that is with the same number of converter units and with identical converter units. However, it is also possible to implement the individual single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) with different numbers of power converter units and/or with different types of power converter units.

In the embodiment shown in FIG. 61, each of the three single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) has the corresponding output coupled to two of the three phases R, S, T. In particular, the first single phase power converter circuit 1 _(R) has its output coupled to the first phase R with the first output node 11 _(R) and to the second phase S with the second output node 12-_(R). The second single phase power converter circuit 1 _(S) has its output coupled to the second phase S with the first output node 11 _(S) and to the third phase T with the second output node 12 _(S), and the third single phase power converter circuit 1 _(T) has its output coupled to the third phase T with the first output node 11 _(T) and to the first phase R with the second output node 12 _(T). In FIG. 61, v1 _(RS) denotes the voltage between the first and second phases R, S, which is the voltage applied to the output of the first single phase converter 1 _(R), v1 _(ST) denotes the voltage between the second and third phases S, T, which is the voltage applied to the output of the second single phase converter 1 _(S), and v1 _(TR) denotes the voltage between the third and first phases T, R, which is the voltage applied to the output of the third single phase converter 1 _(T).

In a conventional 3-phase power supply system, these voltages v1 _(RS), v1 _(ST), v1 _(TR) between two phases are sinusoidal voltages with about 400V_(RMS) or 200V_(RMS) and a phase difference of 120° between two of these voltages v1 _(RS), v1 _(ST), v1 _(TR). The operation of the 3-phase power converter circuit shown in FIG. 61 corresponds to the operation of the 3-phase power converter circuit shown in FIG. 60 with the difference that the synchronization signals (only the synchronization signal S_(Rv1) of the first single phase power converter circuit 1 _(R) is shown in FIG. 61) may be generated based on one of the voltages v1 _(RS), v1 _(ST), v1 _(TR) between two phases instead of one of the voltages v1 _(R), v1 _(S), v1 _(T) between the phases R, S, T and the neutral N.

Like in the embodiment shown in FIG. 60, the output currents i1 _(ROUT), i1 _(SOUT), i1 _(TOUT) can be generated to be alternating currents, such as sinusoidal currents, with the same frequency but different phases. According to one embodiment, a phase difference between these output currents i1 _(ROUT), i1 _(SOUT), i1 _(TOUT) is 120°. Timing diagrams of sinusoidal output currents i1 _(ROUT), i1 _(SOUT), i1 _(TOUT) with a phase difference of 120° correspond to those illustrated in FIG. 62. These currents are suitable to be fed into a 3-phase power grid of the kind explained before and illustrated in FIG. 61.

In the 3-phase power converter circuits shown in FIGS. 60 and 61, each of the individual single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) is coupled to one of three power source circuits 3 _(R), 3 _(S), 3 _(T). Each of these power source circuits 3 _(R), 3 _(S), 3 _(T) includes a plurality of power sources, wherein each of these power sources is coupled to one power converter unit. In FIG. 60, one 3 _(R) of these three power source circuits 3 _(R), 3 _(S), 3 _(T) is shown in detail. This power source circuit 3 _(R) includes three power sources 3 _(R1), 3 _(R2), 3 _(Rn), wherein each of these power sources is coupled to the input of one of the converter units 2 _(R1), 2 _(R2), 2 _(Rn) of the single phase power converter circuit 1 _(R). The other two power source circuits 3 _(S), 3 _(T) that are only schematically illustrated in FIG. 60 can be implemented accordingly. The individual power sources 3 _(R1)-3 _(Rn) can be implemented in accordance with the power source 3 explained herein before. According to one embodiment, the individual power sources 3 _(R1)-3 _(Rn) include PV modules or charge storage devices, such as capacitors or accumulators.

In the 3-phase power converter circuits shown in FIGS. 60 and 61, the individual single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) each receive input power from a corresponding power source circuit 3 _(R), 3 _(S), 3 _(T), so that the individual single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) can be operated independent, with each of these single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) supplying an output current i1 _(ROUT), i1 _(SOUT), i1 _(TOUT) to one of the three phases R, S, T.

FIG. 63 illustrates a further embodiment of a 3-phase power converter circuit. Like the 3-phase power converter circuits shown in FIGS. 60 and 61, the 3-phase power converter circuit shown in FIG. 63 includes three single phase power converter circuits 1 _(R), 1 _(S), 1 _(T), with each of these single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) comprising a plurality of series connected power converter units. The output of each of the three single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) may be coupled to one of the three phases R, S, T of a 3-phase power grid in the way shown in FIG. 60, or the output of each of the three single phase power converter circuits 1 _(R), 1 _(S), i_(T) may be coupled to two of the three phases R, S, T of a 3-phase power grid in the way shown in FIG. 61. Unlike the three single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) shown in FIGS. 60 and 61, the single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) shown in FIG. 63 are coupled to one power source circuit 3 _(R5T) that includes a plurality of power sources 3 ₁, 3 ₂, 3 _(n). These power sources 3 ₁, 3 ₂, 3 _(n) can be implemented in accordance with the power source 3 explained herein before. Each of these power sources 3 ₁, 3 ₂, 3 _(n) is coupled to one power converter unit in each of the three single phase power converter circuits 1 _(R), 1 _(S), 1 _(T). This is illustrated in greater detail in FIG. 64.

FIG. 64 shows one power source 3 of the plurality of power sources 3 ₁-3 _(n) shown in FIG. 63 and shows three power converter units, namely a first power converter unit 2 _(R) that is implemented in the first single phase power converter circuit 1 _(R), a second power converter unit 2 _(S) that is implemented in the second single phase power converter circuit 1 _(S), and a third power converter unit 2 _(T) that is implemented in the third single phase power converter circuit 1 _(T). Other power converter units of the single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) are not shown in FIG. 64.

Each of these power converter units 2 _(R), 2 _(S), 2 _(T) includes an input with two input nodes 21 _(R), 22 _(R), 21 _(S), 22 _(S), and 21 _(T), 22 _(T), respectively. The inputs of the individual power converter units 2 _(R), 2 _(S), 2 _(T) are coupled to the power source 3. Capacitor C3 in FIG. 63 represents an input capacitor of at least one of the three power converter units 2 _(R), 2 _(S), 2 _(T).

According to one embodiment, the individual converter units 2 _(R), 2 _(S), 2 _(T) are implemented in accordance with one of the embodiments shown in FIGS. 44 and 45 (where three converter units 2 ₁, 2 ₂, 2 _(n) are shown). That is, each of the three converter units 2 _(R), 2 _(S), 2 _(T) includes a first converter with a transformer, or includes a first converter unit with or without a transformer and a second converter unit with a transformer. This is schematically illustrated in FIGS. 65 and 68. These figures each show one converter unit that represents one of the converter units 2 _(R), 2 _(S), 2 _(T) shown in FIG. 63. Referring to FIG. 65, each of the converter units 2 _(R), 2 _(S), 2 _(T) can be implemented with a first converter 4 with an isolating topology, which is a converter 4 that includes at least one transformer 84. This converter 4 can be implemented with one of the isolating topologies explained herein before. For example, the converter 4 can be implemented as shown in FIG. 51 and may include a converter stage 80 with a flyback converter topology, an unfolding bridge 85 and an optional EMI filter 88. As explained with reference to FIG. 51, the converter stage 80 generates an output current i80 with a waveform of a rectified alternating signal, and the unfolding bridge generates the output current i1 with the alternating waveform therefrom.

Implementing the converter stage with a flyback converter topology is only an example. A converter stage with any other isolating topology may be used in the converter 4 shown in FIG. 65 as well. Those isolating topologies are, for example, a PS-ZVS converter topology as shown in FIG. 48, an LLC resonant converter topology as shown in FIG. 50, cycloinverter topology, as disclosed in Trubitsyn, or a series resonant converter topology.

FIG. 66 illustrates one embodiment of a converter stage 80 with a series resonant converter topology that can be implemented in the DC/AC converter 4 shown in FIG. 65. The converter stage shown in FIG. 66 includes a series resonant converter topology. This topology is similar to the PS-ZVS converter topology explained with reference to FIG. 48, with the difference that the series resonant converter topology shown in FIG. 66 includes a capacitor 183 instead of an inductor (see reference character 610 in FIG. 48). This capacitor 183 and a primary winding 184 _(P) of a transformer 184 form a series resonant circuit. A first circuit node of this series resonant circuit is coupled to input nodes through a first half-bridge 181 ₁, 181 ₂, and a second circuit node of this series resonant circuit is coupled to input nodes through a second half-bridge 182 ₁, 182 ₂. The input of the converter stage 80 is either coupled to the power source 3 at the input nodes 21, 22, or the output 61, 62 of the optional second converter 6. The transformer includes a secondary winding with two secondary winding sections 184 _(S1), 184 _(S2) and a center tap. A first secondary winding section 184 _(S1) is coupled to output nodes 81, 82, and the output capacitor 89, respectively, via a first rectifier element 185 and an inductor, such as a choke. A second secondary winding section 184 _(S2) is coupled to the output nodes 81, 82, and the output capacitor 89, respectively, via a second rectifier element 186, a third rectifier element 188 and the inductor 187.

A control circuit 189 is configured to control the half-bridges 181 ₁-182 ₂ such that an output current i80 of the converter stage 80 is in correspondence with a reference signal S_(REF). The reference signal S_(REF) is dependent on the synchronization signal (S_(v1) in FIG. 65) and is provided by a controller (see, for example, reference character 5 in FIG. 51) in the way explained herein before. The output current i80 may have the waveform of a rectified alternating signal, wherein either an unfolding bridge in the first converter 4 or a central unfolding bridge in each of the single phase power converter circuits generates an output current with an alternating waveform.

FIG. 67 illustrates a modification of the converter stage 80 shown in FIG. 66. The converter stage 80 shown in FIG. 67 includes a primary winding 184 _(S) with only one primary winding section. In this embodiment, the secondary winding 184 _(S) is coupled to the output nodes 81, 82, and the output capacitor 89, respectively, through a rectifier bridge circuit including four rectifier elements 185 ₁, 185 ₂, 186 ₁, 186 ₂.

As explained with reference to FIG. 51, the first converter (DC/AC converter) 4 may include an unfolding bridge 85. However, it is also possible to omit the unfolding bridge in the first converter 4, and to provide one central unfolding bridge in each of the single phase power converter circuits 1 _(R), 1 _(S), 1 _(T) in accordance with the embodiment disclosed in FIG. 38.

Referring to FIG. 65, each converter unit 2 _(R), 2 _(S), 2 _(T) may additionally include a second converter (DC/DC converter) 6 that is configured to generate a DC voltage V6 supplied to the DC/AC converter 4 from the supply voltage V3 provided by the power source 3. According to one embodiment, the individual converter units 2 _(R), 2 _(S), 2 _(T) coupled to one power source 3 are implemented with identical topologies. According to a further embodiment, these power converter units 2 _(R), 2 _(S), 2 _(T) are implemented with different topologies.

According to one embodiment, the power source 3 includes a PV module. In this case, one of the power converter units 2 _(R), 2 _(S), 2 _(T) is configured to control the input voltage V3 received by the individual converter units 2 _(R), 2 _(S), 2 _(T) such that the PV module is operated in the MPP. This power converter unit may include a second converter unit 6 that is configured to control the input voltage V3.

FIG. 68 illustrates a further embodiment of a power converter unit that can be used to implement the power converter units 2 _(R), 2 _(S), 2 _(T) shown in FIG. 63. The power converter unit 2 _(R), 2 _(S), 2 _(T) shown in FIG. 68 includes a first converter 4 and a second converter 6 coupled between the power source 3 and the first converter 4. The first converter 4 can be implemented in accordance with one of the embodiments explained herein before and may or may not include a transformer (may or may not include an isolating topology). The second converter 6 has an isolating topology and includes a transformer 69. This converter 6 can be implemented in accordance with one of the embodiments explained with reference to FIGS. 47, 48, 49, and 50 herein.

FIG. 69 illustrates a further embodiment of three converter units 2 _(R), 2 _(S), 2 _(T) that are connected to one power source 3. In this embodiment, each of the converter units 2 _(R), 2 _(S), 2 _(T) includes one first converter 4 _(R), 4 _(S), 4 _(T) coupled to the output capacitance C_(R), C_(S), C_(T) of the corresponding converter unit 2 _(R), 2 _(S), 2 _(T) and configured to receive an input voltage V6 _(R), V6 _(S), V6 _(T) from a second converter 6 _(3P). This second converter 6 _(3P) is common to the individual converter units 2 _(R), 2 _(S), 2 _(T) and is coupled between the power source 3 and the individual second converters 4 _(R), 4 _(S), 4 _(T). The second converter 6 _(3P) is configured to generate the three input voltages V6 _(R), V6 _(S), V6 _(T) from the supply voltage V3 provided by the power source 3.

The first converters 4 _(R), 4 _(S), 4 _(T) can be implemented in accordance with one of the embodiments explained herein before. In particular, the individual first converters 4 _(R), 4 _(S), 4 _(T) can be implemented identically or can be implemented with different topologies. According to one embodiment, the individual first converters 4 are implemented with a non-isolating topology, such as the buck boost converter topology explained with reference to FIGS. 54 and 57.

FIG. 70 illustrates one embodiment of the second converter 6 _(3P). Referring to FIG. 70, the second converter 6 _(3P) is implemented as a flyback converter with three rectifier circuits 622 _(R), 622 _(S), 622 _(T), with each of these rectifier circuits 622 _(R), 622 _(S), 622 _(T) providing one of the three input voltages V6 _(R), V6 _(S), V6 _(T) of the first converters 4 _(R), 4 _(S), 4 _(T) (see FIG. 68) between output notes 61 _(R), 62 _(R), 61 _(S), 62 _(S), and 61 _(T), 62 _(T), respectively. The individual rectifier circuits 622 _(R), 622 _(S), 622 _(T) are implemented in accordance with the embodiment shown in FIG. 49. That is, each rectifier circuit includes a rectifier element 713 _(R), 713 _(S), 713 _(T), such as a diode, connected in series with an output capacitor 60 _(R), 60 _(S), 60 _(T). The series circuit with the rectifier element 713 _(R)-713 _(T) and the output capacitor 60 _(R)-60 _(T) is connected in parallel with one of three secondary windings 69 _(SR), 69 _(SS), 69 _(ST) of a transformer 69. The input voltages V6 _(R)-V6 _(T) are available across the output capacitor 60 _(R)-60 _(T).

Referring to FIG. 70 the second converter 6 _(3P) further includes a primary winding 69 _(P) of the transformer 69 and a switching circuit 621. The switching circuit 621 includes a switch 711 connected in series with the primary winding 69 _(P), wherein a series circuit with the primary winding 69 p and the switch 711 is connected between input notes 21, 22 where the supply voltage V3 is available. Like in the embodiments explained herein before, the second converter 6 _(3P) is configured to control the input voltage V3 such that the power source 3 is operated in the MPP. Each of the output voltages V6 _(R)-V6 _(T) provided by the three rectifier circuits 622 _(R)-622 _(S) is received by one of the first converters 4 _(R)-4 _(T) shown in FIG. 69.

In each switching cycle of the switch 711 energy is transferred from the primary winding 69 _(P) to one of the three secondary windings 69 _(SR)-69 _(ST) and the corresponding rectifier circuit 622 _(R)-622 _(T), namely to that rectifier circuit that currently has the lowest output voltage of the three output voltages V6 _(R), V6 _(S), V6 _(T). Supplying energy to the rectifier circuit having the lowest output voltage may result in an increase of this output voltage so that the output voltage of one of the other two rectifier circuits becomes the lowest output voltage, and so that this rectifier now having the lowest output voltage will be supplied. This is a self-regulating process that causes the output voltages V6 _(R)-V6 _(T) of the individual rectifier circuits 622 _(R)-622 _(T) to be substantially equal.

Like a single phase power converter circuit explained with reference to FIGS. 1 to 59 herein before, the 3-phase power converter circuit may include a connection circuit 70 that serves to connect the 3-phase power converter circuit to the power bridge or to disconnect the 3-phase power converter circuit from the power bridge. Referring to FIG. 68, this connection circuit 70 may include four switches 70 _(R), 70 _(S), 70 _(T), 70 _(N), namely one switch connected between each of the three phases R, S, T and a corresponding output of the 3-phase power converter circuit, and one switch between the neutral N and the corresponding outputs of the 3-phase power converter circuit.

In a 3-phase power converter system as disclosed in FIG. 61 where the output of each single phase power converter circuit 1 _(R)-1 _(T) is coupled to two phase, the connection circuit, referring to FIG. 72, may include six switches 70 _(R)-71 _(T), namely one switch between each of the individual output nodes 11 _(R), 11 _(S), 11 _(T), 12 _(R), 12 _(S), 12 _(T) and the corresponding phase R, S, T.

Although various exemplary embodiments of the invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the spirit and scope of the invention. It will be obvious to those reasonably skilled in the art that other components performing the same functions may be suitably substituted. It should be mentioned that features explained with reference to a specific figure may be combined with features of other figures, even in those cases in which this has not explicitly been mentioned. Further, the methods of the invention may be achieved in either all software implementations, using the appropriate processor instructions, or in hybrid implementations that utilize a combination of hardware logic and software logic to achieve the same results. Such modifications to the inventive concept are intended to be covered by the appended claims.

Spatially relative terms such as “under,” “below,” “lower,” “over,” “upper” and the like, are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first,” “second” and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.

As used herein, the terms “having,” “containing,” “including,” “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a,” “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise. 

What is claimed is:
 1. A multiphase power converter circuit, comprising a plurality of single phase power converter circuits, wherein each single phase power converter circuit comprises: a converter series circuit comprising a plurality of converter units, the converter series circuit configured to output a series circuit output current; and a synchronization circuit configured to generate at least one synchronization signal; wherein at least one of the plurality of converter units is configured to generate an output current such that a frequency or a phase of the output current is dependent on the synchronization signal, wherein the synchronization circuit comprises a series circuit with a plurality of measurement units coupled to the converter series circuit, wherein each measurement unit is configured to output one synchronization signal, and wherein each converter unit is configured to receive one of the synchronization signals output by the plurality of measurement units.
 2. The power converter circuit of claim 1, wherein each of the plurality of converter units comprises an input configured to be coupled to a power source.
 3. The multiphase power converter circuit of claim 1, wherein each single phase power converter circuit is configured to receive an external voltage; and wherein the synchronization circuit is configured to generate the synchronization signal dependent on a voltage level of the external voltage.
 4. The multiphase power converter circuit of claim 3, wherein the synchronization circuit is configured to generate the synchronization signal such that there is a phase difference between the external voltage and the synchronization signal.
 5. The multiphase power converter circuit of claim 1, wherein each single phase power converter circuit is configured to receive an external alternating voltage, and wherein the synchronization circuit is configured to generate the synchronization signal as a rectified alternating signal dependent on the external alternating voltage.
 6. The multiphase power converter circuit of claim 5, wherein each single phase power converter circuit further comprises: an unfolding circuit coupled to the converter series circuit and configured to convert the series circuit output current into an alternating output current.
 7. The multiphase power converter circuit of claim 1, wherein the synchronization circuit comprises a series circuit with a plurality of measurement units coupled to the converter series circuit, wherein each measurement unit is configured to output one synchronization signal, and wherein each converter unit is configured to receive one of the synchronization signals output by the plurality of measurement units.
 8. The multiphase power converter circuit of claim 7, wherein the synchronization signal provided by each of the plurality of measurement units is a voltage across the measurement unit or is a fraction thereof.
 9. The multiphase power converter circuit of claim 1, wherein the converter unit comprises a first converter configured to receive a direct voltage and to output the output current.
 10. The multiphase power converter circuit of claim 9, wherein the first converter is configured to generate the output current dependent on a first reference signal, and wherein the first reference signal is dependent on the at least one synchronization signal and the output current.
 11. The multiphase power converter circuit of claim 10, wherein the converter unit further comprises a control circuit configured to generate the first reference signal dependent on the at least one synchronization signal and the output current.
 12. The multiphase power converter circuit of claim 11, wherein the first converter is configured to receive an input voltage, and wherein the control circuit is configured to generate the first reference signal dependent on the input voltage.
 13. The multiphase power converter circuit of claim 9, wherein the first converter comprises: a converter stage configured to receive the direct voltage and to output a rectified alternating current; and an unfolding circuit configured to receive the rectified alternating current and to output the output current.
 14. The multiphase power converter circuit of claim 13, wherein the converter stage comprises an isolating topology.
 15. The multiphase power converter circuit of claim 13, wherein the converter stage comprises a topology selected from the group consisting of: a flyback converter topology; a two-transistor forward (TTF) converter topology; a series resonant converter topology; a phase-shift zero-voltage switching (PS ZVS) converter topology; an LLC converter topology; and a cycloinverter topology.
 16. The multiphase power converter circuit of claim 13, wherein the converter stage is configured to generate the rectified alternating current with a frequency and a phase that is dependent on the synchronization signal.
 17. The multiphase power converter circuit of claim 9, wherein the converter unit further comprises: an input configured to be coupled to a power source; and a second converter coupled between the input of the one of the converter units and the first converter.
 18. The multiphase power converter circuit of claim 17, wherein the second converter is configured to adjust an input signal at the input dependent on a second reference signal.
 19. The multiphase power converter circuit of claim 18, wherein the input signal is one of an input voltage and an input current.
 20. The multiphase power converter circuit of claim 18, further comprising: maximum power point tracker configured to generate the second reference signal dependent on an input voltage and an input current of the second converter.
 21. The multiphase power converter circuit of claim 18, wherein the first converter comprises a topology selected from a group consisting of: a buck converter topology; a boost converter topology; a buck-boost converter; a boost-buck converter; and an inverting buck-boost topology.
 22. The multiphase power converter circuit of claim 21, wherein the first converter comprises the boost converter topology.
 23. The multiphase power converter circuit of claim 18, wherein the second converter comprises a topology selected from a group consisting of: a flyback converter topology; a two-transistor forward (TTF) converter topology; a series resonant converter topology; a phase-shift zero-voltage switching (PS ZVS) converter topology; an LLC converter topology; and a cycloinverter topology.
 24. The multiphase power converter circuit of claim 18, wherein the second converter comprises at least two converter stages connected in parallel.
 25. The multiphase power converter circuit of claim 18, wherein the second converter comprises a full-bridge topology.
 26. The multiphase power converter circuit of claim 1, wherein the converter unit comprises an output capacitor coupled between output terminals, and wherein the output current is a current into a circuit node common to the output capacitor and one of the output terminals.
 27. A multiphase power converter circuit, comprising a plurality of single phase power converter circuits, wherein each single phase power converter circuit comprises: a converter series circuit comprising a plurality of converter units, the converter series circuit configured to output a series circuit output current; and a synchronization circuit configured to generate at least one synchronization signal; wherein at least one of the plurality of converter units is configured to generate an output current such that a frequency or a phase of the output current is dependent on the synchronization signal, wherein each of the plurality of converter units comprises an input configured to be coupled to a power source, wherein there is a group of converter units that includes one converter unit in each of the single phase power converter circuits, and wherein the converter units of the group of converter units are configured to be coupled to one common power source.
 28. The multiphase power converter circuit of claim 27, wherein each of the converter units of the group of converter units comprises a first converter configured to output the output current, and wherein the group of converter units comprises a second converter coupled between the common power source and the first converter.
 29. The multiphase power converter circuit of claim 28, wherein each converter unit of the group of converter units comprises the second converter coupled between the common power source and the first converter.
 30. The multiphase power converter circuit of claim 29, wherein the second converter of one of the converter units of the group of converter units is configured to adjust at least one of an input voltage, and an input current received from the power source.
 31. The multiphase power converter circuit of claim 28, wherein the group of converter units comprises only the second converter coupled between the common power source and the first converter in each of the converter units of the group of converter units.
 32. The multiphase power converter circuit of claim 28, wherein the second converter comprises an isolating topology.
 33. The multiphase power converter circuit of claim 28, wherein the second converter comprises a transformer.
 34. A multiphase power converter circuit, comprising a plurality of single phase power converter circuits, wherein each single phase power converter circuit comprises: a converter series circuit comprising a plurality of converter units, the converter series circuit configured to output a series circuit output current; and a synchronization circuit configured to generate at least one synchronization signal; wherein at least one of the plurality of converter units is configured to generate an output current such that a frequency or a phase of the output current is dependent on the synchronization signal, wherein the converter unit comprises a signal generator configured to generate a continuous synchronization signal from the synchronization signal and to generate the output current such that at least one of a frequency and a phase of the output current is dependent on the continuous synchronization signal.
 35. The multiphase power converter circuit of claim 34, wherein the synchronization signal is an alternating signal, wherein the signal generator is configured to receive the synchronization signal for a given time period, to detect a frequency and a phase of the synchronization signal, and to generate the continuous synchronization signal dependent on the detected frequency and phase.
 36. The power converter circuit of claim 34, wherein the synchronization signal is a pulsed signal comprising a plurality of signal pulses, wherein the signal generator is configured to generate the continuous synchronization signal with a frequency and a phase dependent on the frequency and the phase of the pulsed signal. 